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648 lines
15 KiB
648 lines
15 KiB
/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __KGSL_HFI_H
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#define __KGSL_HFI_H
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#include <linux/types.h>
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#define HFI_QUEUE_SIZE SZ_4K /* bytes, must be base 4dw */
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#define MAX_RCVD_PAYLOAD_SIZE 16 /* dwords */
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#define MAX_RCVD_SIZE (MAX_RCVD_PAYLOAD_SIZE + 3) /* dwords */
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#define HFI_MAX_MSG_SIZE (SZ_1K>>2) /* dwords */
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/* Below section is for all structures related to HFI queues */
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#define HFI_QUEUE_DEFAULT_CNT 3
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#define HFI_QUEUE_DISPATCH_CNT 1
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#define HFI_QUEUE_MAX (HFI_QUEUE_DEFAULT_CNT + HFI_QUEUE_DISPATCH_CNT)
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struct hfi_queue_table;
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/* Total header sizes + queue sizes + 16 for alignment */
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#define HFIMEM_SIZE (sizeof(struct hfi_queue_table) + 16 + \
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(HFI_QUEUE_SIZE * HFI_QUEUE_MAX))
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#define HFI_CMD_ID 0
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#define HFI_MSG_ID 1
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#define HFI_DBG_ID 2
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#define HFI_DSP_ID_0 3
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#define HFI_CMD_IDX 0
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#define HFI_MSG_IDX 1
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#define HFI_DBG_IDX 2
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#define HFI_DSP_IDX_BASE 3
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#define HFI_DSP_IDX_0 3
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#define HFI_CMD_IDX_LEGACY 0
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#define HFI_DSP_IDX_0_LEGACY 1
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#define HFI_MSG_IDX_LEGACY 4
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#define HFI_DBG_IDX_LEGACY 5
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#define HFI_QUEUE_STATUS_DISABLED 0
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#define HFI_QUEUE_STATUS_ENABLED 1
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/* HTOF queue priority, 1 is highest priority */
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#define HFI_CMD_PRI 10
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#define HFI_MSG_PRI 10
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#define HFI_DBG_PRI 40
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#define HFI_DSP_PRI_0 20
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#define HFI_RSP_TIMEOUT 100 /* msec */
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#define HFI_H2F_CMD_IRQ_MASK BIT(0)
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#define HFI_IRQ_MSGQ_MASK BIT(0)
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#define HFI_IRQ_SIDEMSGQ_MASK BIT(1)
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#define HFI_IRQ_DBGQ_MASK BIT(2)
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#define HFI_IRQ_CM3_FAULT_MASK BIT(15)
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#define HFI_IRQ_OOB_MASK GENMASK(31, 16)
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#define HFI_IRQ_MASK (HFI_IRQ_SIDEMSGQ_MASK |\
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HFI_IRQ_DBGQ_MASK |\
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HFI_IRQ_CM3_FAULT_MASK)
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#define CLKSET_OPTION_DEFAULT 0
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#define CLKSET_OPTION_CLOSEST 1
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#define CLKSET_OPTION_ATMOST 2
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#define CLKSET_OPTION_ATLEAST 3
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#define DCVS_ACK_NONBLOCK 0
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#define DCVS_ACK_BLOCK 1
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#define HFI_FEATURE_DCVS 0
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#define HFI_FEATURE_ECP 1
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#define HFI_FEATURE_PREEMPTION 2
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#define HFI_FEATURE_CLOCKS_ON 3
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#define HFI_FEATURE_BUS_ON 4
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#define HFI_FEATURE_RAIL_ON 5
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#define HFI_FEATURE_HWCG 6
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#define HFI_FEATURE_LM 7
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#define HFI_FEATURE_THROTTLE 8
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#define HFI_FEATURE_IFPC 9
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#define HFI_FEATURE_NAP 10
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#define HFI_FEATURE_BCL 11
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#define HFI_FEATURE_ACD 12
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#define HFI_FEATURE_DIDT 13
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#define HFI_VALUE_FT_POLICY 100
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#define HFI_VALUE_RB_MAX_CMDS 101
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#define HFI_VALUE_CTX_MAX_CMDS 102
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#define HFI_VALUE_ADDRESS 103
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#define HFI_VALUE_MAX_GPU_PERF_INDEX 104
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#define HFI_VALUE_MIN_GPU_PERF_INDEX 105
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#define HFI_VALUE_MAX_BW_PERF_INDEX 106
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#define HFI_VALUE_MIN_BW_PERF_INDEX 107
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#define HFI_VALUE_MAX_GPU_THERMAL_INDEX 108
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#define HFI_VALUE_GPUCLK 109
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#define HFI_VALUE_CLK_TIME 110
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#define HFI_VALUE_LOG_LEVEL 111
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#define HFI_VALUE_LOG_EVENT_ON 112
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#define HFI_VALUE_LOG_EVENT_OFF 113
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#define HFI_VALUE_DCVS_OBJ 114
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#define HFI_VALUE_GLOBAL_TOKEN 0xFFFFFFFF
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/**
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* struct hfi_queue_table_header - HFI queue table structure
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* @version: HFI protocol version
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* @size: queue table size in dwords
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* @qhdr0_offset: first queue header offset (dwords) in this table
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* @qhdr_size: queue header size
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* @num_q: number of queues defined in this table
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* @num_active_q: number of active queues
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*/
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struct hfi_queue_table_header {
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uint32_t version;
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uint32_t size;
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uint32_t qhdr0_offset;
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uint32_t qhdr_size;
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uint32_t num_q;
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uint32_t num_active_q;
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};
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/**
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* struct hfi_queue_header - HFI queue header structure
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* @status: active: 1; inactive: 0
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* @start_addr: starting address of the queue in GMU VA space
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* @type: queue type encoded the priority, ID and send/recevie types
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* @queue_size: size of the queue
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* @msg_size: size of the message if each message has fixed size.
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* Otherwise, 0 means variable size of message in the queue.
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* @drop_cnt: count of dropped messages
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* @rx_wm: receiver watermark
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* @tx_wm: sender watermark
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* @rx_req: receiver request
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* @tx_req: sender request
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* @read_index: read index of the queue
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* @write_index: write index of the queue
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*/
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struct hfi_queue_header {
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uint32_t status;
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uint32_t start_addr;
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uint32_t type;
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uint32_t queue_size;
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uint32_t msg_size;
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uint32_t drop_cnt;
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uint32_t rx_wm;
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uint32_t tx_wm;
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uint32_t rx_req;
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uint32_t tx_req;
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uint32_t read_index;
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uint32_t write_index;
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};
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struct hfi_queue_table {
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struct hfi_queue_table_header qtbl_hdr;
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struct hfi_queue_header qhdr[HFI_QUEUE_MAX];
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};
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enum hfi_msg_type {
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HFI_MSG_CMD = 0, /* V1 and V2 */
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HFI_MSG_ACK = 1, /* V2 only */
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HFI_V1_MSG_POST = 1, /* V1 only */
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HFI_V1_MSG_ACK = 2, /* V1 only */
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};
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#define H2F_MSG_INIT 0
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#define H2F_MSG_FW_VER 1
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#define H2F_MSG_LM_CFG 2
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#define H2F_MSG_BW_VOTE_TBL 3
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#define H2F_MSG_PERF_TBL 4
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#define H2F_MSG_TEST 5
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#define H2F_MSG_ACD_TBL 7
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#define H2F_MSG_START 10
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#define H2F_MSG_FEATURE_CTRL 11
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#define H2F_MSG_GET_VALUE 12
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#define H2F_MSG_SET_VALUE 13
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#define H2F_MSG_CORE_FW_START 14
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#define F2H_MSG_MEM_ALLOC 20
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#define H2F_MSG_GX_BW_PERF_VOTE 30
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#define H2F_MSG_FW_HALT 32
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#define H2F_MSG_PREPARE_SLUMBER 33
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#define F2H_MSG_ERR 100
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#define F2H_MSG_DEBUG 101
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#define F2H_MSG_GMU_CNTR_REGISTER 110
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#define F2H_MSG_GMU_CNTR_RELEASE 111
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#define F2H_MSG_ACK 126 /* Deprecated for v2.0*/
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#define H2F_MSG_ACK 127 /* Deprecated for v2.0*/
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#define H2F_MSG_REGISTER_CONTEXT 128
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#define H2F_MSG_UNREGISTER_CONTEXT 129
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#define H2F_MSG_ISSUE_CMD 130
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#define H2F_MSG_ISSUE_CMD_RAW 131
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#define H2F_MSG_TS_NOTIFY 132
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#define F2H_MSG_TS_RETIRE 133
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#define H2F_MSG_CONTEXT_POINTERS 134
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#define H2F_MSG_CONTEXT_RULE 140 /* AKA constraint */
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#define F2H_MSG_CONTEXT_BAD 150
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/* H2F */
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struct hfi_gmu_init_cmd {
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uint32_t hdr;
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uint32_t seg_id;
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uint32_t dbg_buffer_addr;
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uint32_t dbg_buffer_size;
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uint32_t boot_state;
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};
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/* H2F */
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struct hfi_fw_version_cmd {
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uint32_t hdr;
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uint32_t supported_ver;
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};
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/* H2F */
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struct hfi_lmconfig_cmd {
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uint32_t hdr;
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uint32_t limit_conf;
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uint32_t bcl_conf;
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uint32_t lm_enable_bitmask;
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};
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#define ARC_VOTE_GET_PRI(_v) ((_v) & 0xFF)
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#define ARC_VOTE_GET_SEC(_v) (((_v) >> 8) & 0xFF)
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#define ARC_VOTE_GET_VLVL(_v) (((_v) >> 16) & 0xFFFF)
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#define ARC_VOTE_SET(pri, sec, vlvl) \
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((((vlvl) & 0xFFFF) << 16) | (((sec) & 0xFF) << 8) | ((pri) & 0xFF))
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/* H2F */
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struct hfi_bwtable_cmd {
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uint32_t hdr;
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uint32_t bw_level_num;
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uint32_t cnoc_cmds_num;
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uint32_t ddr_cmds_num;
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uint32_t cnoc_wait_bitmask;
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uint32_t ddr_wait_bitmask;
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uint32_t cnoc_cmd_addrs[MAX_CNOC_CMDS];
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uint32_t cnoc_cmd_data[MAX_CNOC_LEVELS][MAX_CNOC_CMDS];
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uint32_t ddr_cmd_addrs[MAX_BW_CMDS];
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uint32_t ddr_cmd_data[MAX_GX_LEVELS][MAX_BW_CMDS];
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};
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struct opp_gx_desc {
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uint32_t vote;
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uint32_t acd;
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uint32_t freq;
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};
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struct opp_desc {
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uint32_t vote;
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uint32_t freq;
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};
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/* H2F */
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struct hfi_dcvstable_v1_cmd {
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uint32_t hdr;
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uint32_t gpu_level_num;
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uint32_t gmu_level_num;
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struct opp_desc gx_votes[MAX_GX_LEVELS];
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struct opp_desc cx_votes[MAX_CX_LEVELS];
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};
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/* H2F */
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struct hfi_dcvstable_cmd {
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uint32_t hdr;
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uint32_t gpu_level_num;
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uint32_t gmu_level_num;
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struct opp_gx_desc gx_votes[MAX_GX_LEVELS];
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struct opp_desc cx_votes[MAX_CX_LEVELS];
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};
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#define HFI_ACD_INIT_VERSION 1
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#define MAX_ACD_STRIDE 2
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#define MAX_ACD_NUM_LEVELS 6
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/* H2F */
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struct hfi_acd_table_cmd {
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uint32_t hdr;
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uint32_t version;
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uint32_t enable_by_level;
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uint32_t stride;
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uint32_t num_levels;
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uint32_t data[MAX_ACD_NUM_LEVELS * MAX_ACD_STRIDE];
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};
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/* H2F */
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struct hfi_test_cmd {
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uint32_t hdr;
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uint32_t data;
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};
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/* H2F */
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struct hfi_start_cmd {
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uint32_t hdr;
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};
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/* H2F */
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struct hfi_feature_ctrl_cmd {
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uint32_t hdr;
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uint32_t feature;
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uint32_t enable;
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uint32_t data;
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};
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/* H2F */
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struct hfi_get_value_cmd {
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uint32_t hdr;
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uint32_t type;
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uint32_t subtype;
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};
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/* Internal */
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struct hfi_get_value_req {
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struct hfi_get_value_cmd cmd;
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uint32_t data[16];
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};
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/* F2H */
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struct hfi_get_value_reply_cmd {
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uint32_t hdr;
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uint32_t req_hdr;
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uint32_t data[16];
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};
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/* H2F */
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struct hfi_set_value_cmd {
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uint32_t hdr;
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uint32_t type;
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uint32_t subtype;
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uint32_t data;
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};
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/* H2F */
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struct hfi_core_fw_start_cmd {
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uint32_t hdr;
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uint32_t handle;
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};
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/* CP/GFX pipeline can access, The mem_kind may imply restrictions for non-CP */
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#define MEMFLAG_GFX_ACC BIT(0)
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/* Buffer has APRIV protection in GFX PTEs */
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#define MEMFLAG_GFX_PRIV BIT(1)
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/* Buffer is read-write for GFX PTEs. A 0 indicates read-only */
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#define MEMFLAG_GFX_WRITEABLE BIT(2)
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/* GMU can access */
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#define MEMFLAG_GMU_ACC BIT(3)
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/* Buffer has APRIV protection in GMU PTEs */
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#define MEMFLAG_GMU_PRIV BIT(4)
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/* Buffer is read-write for GMU PTEs. A 0 indicates read-only */
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#define MEMFLAG_GMU_WRITEABLE BIT(5)
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/* Buffer is located in GMU's non-cached bufferable VA range */
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#define MEMFLAG_GMU_BUFFERABLE BIT(6)
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/* Buffer is located in GMU's cacheable VA range */
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#define MEMFLAG_GMU_CACHEABLE BIT(7)
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/* Host can access */
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#define MEMFLAG_HOST_ACC BIT(8)
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/*
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* Request that Host initialize the buffer.
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* Implies zero-init, unless Memkind implies otherwise
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*/
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#define MEMFLAG_HOST_INIT BIT(9)
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#define HFI_MEMKIND_GENERIC 0
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#define HFI_MEMKIND_RB 1
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#define HFI_MEMKIND_MEMSTORE 2
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#define HFI_MEMKIND_CSW_SMMU_INFO 3
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#define HFI_MEMKIND_CSW_PRIV_NON_SECURE 4
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#define HFI_MEMKIND_CSW_PRIV_SECURE 5
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#define HFI_MEMKIND_CSW_NON_PRIV 6
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#define HFI_MEMKIND_CSW_COUNTER 7
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#define HFI_MEMKIND_CTXTREC_PERF_CNTR_SAVE_RESTORE 8
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#define HFI_MEMKIND_CTXTREC_PREEMPT_CNTR 9
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#define HFI_MEMKIND_SYS_LOG 10
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#define HFI_MEMKIND_CRASH_DUMP 11
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#define HFI_MEMKIND_MMIO_DPU 12
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#define HFI_MEMKIND_MMIO_TCSR 13
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#define HFI_MEMKIND_MMIO_QDSS_STM 14
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struct hfi_mem_alloc_desc {
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uint64_t gpu_addr;
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uint32_t flags;
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uint32_t mem_kind;
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uint32_t host_mem_handle;
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uint32_t gmu_mem_handle;
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uint32_t gmu_addr;
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uint32_t size; /* Bytes */
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};
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/* F2H */
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struct hfi_mem_alloc_cmd {
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uint32_t hdr;
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uint32_t reserved; /* Padding to ensure alignment of 'desc' below */
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struct hfi_mem_alloc_desc desc;
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};
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/* H2F */
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struct hfi_mem_alloc_reply_cmd {
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uint32_t hdr;
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uint32_t req_hdr;
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struct hfi_mem_alloc_desc desc;
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};
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/* H2F */
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struct hfi_gx_bw_perf_vote_cmd {
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uint32_t hdr;
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uint32_t ack_type;
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uint32_t freq;
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uint32_t bw;
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};
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/* H2F */
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struct hfi_fw_halt_cmd {
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uint32_t hdr;
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uint32_t en_halt;
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};
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/* H2F */
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struct hfi_prep_slumber_cmd {
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uint32_t hdr;
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uint32_t bw;
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uint32_t freq;
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};
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/* F2H */
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struct hfi_err_cmd {
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uint32_t hdr;
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uint32_t error_code;
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uint32_t data[16];
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};
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/* F2H */
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struct hfi_debug_cmd {
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uint32_t hdr;
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uint32_t type;
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uint32_t timestamp;
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uint32_t data;
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};
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/* F2H */
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struct hfi_gmu_cntr_register_cmd {
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uint32_t hdr;
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uint32_t group_id;
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uint32_t countable;
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};
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/* H2F */
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struct hfi_gmu_cntr_register_reply_cmd {
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uint32_t hdr;
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uint32_t req_hdr;
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uint32_t group_id;
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uint32_t countable;
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uint64_t counter_addr;
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};
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/* F2H */
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struct hfi_gmu_cntr_release_cmd {
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uint32_t hdr;
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uint32_t group_id;
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uint32_t countable;
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};
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#define CTXT_FLAG_PMODE 0x00000001
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#define CTXT_FLAG_SWITCH_INTERNAL 0x00000002
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#define CTXT_FLAG_SWITCH 0x00000008
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#define CTXT_FLAG_NOTIFY 0x00000020
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#define CTXT_FLAG_NO_FAULT_TOLERANCE 0x00000200
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#define CTXT_FLAG_PWR_RULE 0x00000800
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#define CTXT_FLAG_PRIORITY_MASK 0x0000F000
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#define CTXT_FLAG_IFH_NOP 0x00010000
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#define CTXT_FLAG_SECURE 0x00020000
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#define CTXT_FLAG_TYPE_MASK 0x01F00000
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#define CTXT_FLAG_TYPE_SHIFT 20
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#define CTXT_FLAG_TYPE_ANY 0
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#define CTXT_FLAG_TYPE_GL 1
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#define CTXT_FLAG_TYPE_CL 2
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#define CTXT_FLAG_TYPE_C2D 3
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#define CTXT_FLAG_TYPE_RS 4
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#define CTXT_FLAG_TYPE_UNKNOWN 0x1E
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#define CTXT_FLAG_PREEMPT_STYLE_MASK 0x0E000000
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#define CTXT_FLAG_PREEMPT_STYLE_SHIFT 25
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#define CTXT_FLAG_PREEMPT_STYLE_ANY 0
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#define CTXT_FLAG_PREEMPT_STYLE_RB 1
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#define CTXT_FLAG_PREEMPT_STYLE_FG 2
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/* H2F */
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struct hfi_register_ctxt_cmd {
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uint32_t hdr;
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uint32_t ctxt_id;
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uint32_t flags;
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uint64_t pt_addr;
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uint32_t ctxt_idr;
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uint32_t ctxt_bank;
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};
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/* H2F */
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struct hfi_unregister_ctxt_cmd {
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uint32_t hdr;
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uint32_t ctxt_id;
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uint32_t ts;
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};
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#define CMDBATCH_SWITCH CTXT_FLAG_SWITCH
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#define CMDBATCH_NOTIFY CTXT_FLAG_NOTIFY
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#define CMDBATCH_PROFILING 0x00000010
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#define CMDBATCH_EOF 0x00000100
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#define CMDBATCH_PWR_STRICT CTXT_FLAG_PWR_RULE
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struct hfi_issue_ib {
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uint64_t addr;
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uint32_t size;
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};
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|
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/* H2F */
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struct hfi_issue_cmd_cmd {
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uint32_t hdr;
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uint32_t ctxt_id;
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uint32_t flags;
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uint32_t ts;
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uint32_t count;
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struct hfi_issue_ib *ibs[];
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};
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/* Internal */
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struct hfi_issue_cmd_req {
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uint32_t queue;
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uint32_t ctxt_id;
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struct hfi_issue_cmd_cmd cmd;
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};
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|
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/* H2F */
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/* The length of *buf will be embedded in the hdr */
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struct hfi_issue_cmd_raw_cmd {
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|
uint32_t hdr;
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|
uint32_t *buf;
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|
};
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|
|
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/* Internal */
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|
struct hfi_issue_cmd_raw_req {
|
|
uint32_t queue;
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|
uint32_t ctxt_id;
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|
uint32_t len;
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|
uint32_t *buf;
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|
};
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|
|
|
/* H2F */
|
|
struct hfi_ts_notify_cmd {
|
|
uint32_t hdr;
|
|
uint32_t ctxt_id;
|
|
uint32_t ts;
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|
};
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|
|
|
#define TS_RETIRE_FLUSH 1
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|
#define TS_RETIRE_ERROR 2
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|
#define TS_RETIRE_PAST 3
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|
#define TS_RETIRE_DONE 4
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|
|
|
/* F2H */
|
|
struct hfi_ts_retire_cmd {
|
|
uint32_t hdr;
|
|
uint32_t ctxt_id;
|
|
uint32_t ts;
|
|
uint32_t type;
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|
};
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|
|
|
/* H2F */
|
|
struct hfi_context_pointers_cmd {
|
|
uint32_t hdr;
|
|
uint32_t ctxt_id;
|
|
uint64_t sop_addr;
|
|
uint64_t eop_addr;
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|
};
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|
|
|
/* H2F */
|
|
struct hfi_context_rule_cmd {
|
|
uint32_t hdr;
|
|
uint32_t ctxt_id;
|
|
uint32_t type;
|
|
uint32_t status;
|
|
};
|
|
|
|
/* F2H */
|
|
struct hfi_context_bad_cmd {
|
|
uint32_t hdr;
|
|
uint32_t ctxt_id;
|
|
uint32_t status;
|
|
uint32_t error;
|
|
};
|
|
|
|
/* H2F */
|
|
struct hfi_context_bad_reply_cmd {
|
|
uint32_t hdr;
|
|
uint32_t req_hdr;
|
|
};
|
|
|
|
/**
|
|
* struct pending_cmd - data structure to track outstanding HFI
|
|
* command messages
|
|
* @sent_hdr: copy of outgoing header for response comparison
|
|
* @results: the payload of received return message (ACK)
|
|
*/
|
|
struct pending_cmd {
|
|
uint32_t sent_hdr;
|
|
uint32_t results[MAX_RCVD_SIZE];
|
|
};
|
|
|
|
/**
|
|
* struct kgsl_hfi - HFI control structure
|
|
* @kgsldev: Point to the kgsl device
|
|
* @hfi_interrupt_num: number of GMU asserted HFI interrupt
|
|
* @cmdq_mutex: mutex to protect command queue access from multiple senders
|
|
* @tasklet: the thread handling received messages from GMU
|
|
* @version: HFI version number provided
|
|
* @seqnum: atomic counter that is incremented for each message sent. The
|
|
* value of the counter is used as sequence number for HFI message
|
|
* @bwtbl_cmd: HFI BW table buffer
|
|
* @acd_tbl_cmd: HFI table for ACD data
|
|
*/
|
|
struct kgsl_hfi {
|
|
struct kgsl_device *kgsldev;
|
|
int hfi_interrupt_num;
|
|
struct mutex cmdq_mutex;
|
|
struct tasklet_struct tasklet;
|
|
uint32_t version;
|
|
atomic_t seqnum;
|
|
struct hfi_bwtable_cmd bwtbl_cmd;
|
|
struct hfi_acd_table_cmd acd_tbl_cmd;
|
|
};
|
|
|
|
struct gmu_device;
|
|
struct gmu_memdesc;
|
|
|
|
irqreturn_t hfi_irq_handler(int irq, void *data);
|
|
int hfi_start(struct kgsl_device *device, struct gmu_device *gmu,
|
|
uint32_t boot_state);
|
|
void hfi_stop(struct gmu_device *gmu);
|
|
void hfi_receiver(unsigned long data);
|
|
void hfi_init(struct kgsl_hfi *hfi, struct gmu_memdesc *mem_addr,
|
|
uint32_t queue_sz_bytes);
|
|
|
|
/* hfi_send_req is only for external (to HFI) requests */
|
|
int hfi_send_req(struct gmu_device *gmu, unsigned int id, void *data);
|
|
#endif /* __KGSL_HFI_H */
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