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272 lines
6.6 KiB
272 lines
6.6 KiB
/*
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* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "edp.h"
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#include "edp.xml.h"
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#define AUX_CMD_FIFO_LEN 144
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#define AUX_CMD_NATIVE_MAX 16
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#define AUX_CMD_I2C_MAX 128
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#define EDP_INTR_AUX_I2C_ERR \
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(EDP_INTERRUPT_REG_1_WRONG_ADDR | EDP_INTERRUPT_REG_1_TIMEOUT | \
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EDP_INTERRUPT_REG_1_NACK_DEFER | EDP_INTERRUPT_REG_1_WRONG_DATA_CNT | \
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EDP_INTERRUPT_REG_1_I2C_NACK | EDP_INTERRUPT_REG_1_I2C_DEFER)
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#define EDP_INTR_TRANS_STATUS \
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(EDP_INTERRUPT_REG_1_AUX_I2C_DONE | EDP_INTR_AUX_I2C_ERR)
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struct edp_aux {
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void __iomem *base;
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bool msg_err;
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struct completion msg_comp;
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/* To prevent the message transaction routine from reentry. */
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struct mutex msg_mutex;
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struct drm_dp_aux drm_aux;
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};
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#define to_edp_aux(x) container_of(x, struct edp_aux, drm_aux)
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static int edp_msg_fifo_tx(struct edp_aux *aux, struct drm_dp_aux_msg *msg)
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{
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u32 data[4];
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u32 reg, len;
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bool native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ);
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bool read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
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u8 *msgdata = msg->buffer;
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int i;
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if (read)
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len = 4;
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else
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len = msg->size + 4;
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/*
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* cmd fifo only has depth of 144 bytes
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*/
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if (len > AUX_CMD_FIFO_LEN)
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return -EINVAL;
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/* Pack cmd and write to HW */
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data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */
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if (read)
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data[0] |= BIT(4); /* R/W */
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data[1] = (msg->address >> 8) & 0xff; /* addr[15:8] */
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data[2] = msg->address & 0xff; /* addr[7:0] */
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data[3] = (msg->size - 1) & 0xff; /* len[7:0] */
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for (i = 0; i < len; i++) {
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reg = (i < 4) ? data[i] : msgdata[i - 4];
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reg = EDP_AUX_DATA_DATA(reg); /* index = 0, write */
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if (i == 0)
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reg |= EDP_AUX_DATA_INDEX_WRITE;
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edp_write(aux->base + REG_EDP_AUX_DATA, reg);
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}
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reg = 0; /* Transaction number is always 1 */
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if (!native) /* i2c */
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reg |= EDP_AUX_TRANS_CTRL_I2C;
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reg |= EDP_AUX_TRANS_CTRL_GO;
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edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, reg);
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return 0;
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}
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static int edp_msg_fifo_rx(struct edp_aux *aux, struct drm_dp_aux_msg *msg)
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{
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u32 data;
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u8 *dp;
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int i;
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u32 len = msg->size;
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edp_write(aux->base + REG_EDP_AUX_DATA,
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EDP_AUX_DATA_INDEX_WRITE | EDP_AUX_DATA_READ); /* index = 0 */
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dp = msg->buffer;
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/* discard first byte */
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data = edp_read(aux->base + REG_EDP_AUX_DATA);
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for (i = 0; i < len; i++) {
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data = edp_read(aux->base + REG_EDP_AUX_DATA);
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dp[i] = (u8)((data >> 8) & 0xff);
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}
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return 0;
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}
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/*
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* This function does the real job to process an AUX transaction.
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* It will call msm_edp_aux_ctrl() function to reset the AUX channel,
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* if the waiting is timeout.
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* The caller who triggers the transaction should avoid the
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* msm_edp_aux_ctrl() running concurrently in other threads, i.e.
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* start transaction only when AUX channel is fully enabled.
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*/
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static ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux,
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struct drm_dp_aux_msg *msg)
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{
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struct edp_aux *aux = to_edp_aux(drm_aux);
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ssize_t ret;
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unsigned long time_left;
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bool native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ);
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bool read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
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/* Ignore address only message */
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if ((msg->size == 0) || (msg->buffer == NULL)) {
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msg->reply = native ?
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DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
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return msg->size;
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}
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/* msg sanity check */
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if ((native && (msg->size > AUX_CMD_NATIVE_MAX)) ||
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(msg->size > AUX_CMD_I2C_MAX)) {
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pr_err("%s: invalid msg: size(%zu), request(%x)\n",
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__func__, msg->size, msg->request);
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return -EINVAL;
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}
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mutex_lock(&aux->msg_mutex);
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aux->msg_err = false;
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reinit_completion(&aux->msg_comp);
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ret = edp_msg_fifo_tx(aux, msg);
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if (ret < 0)
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goto unlock_exit;
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DBG("wait_for_completion");
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time_left = wait_for_completion_timeout(&aux->msg_comp,
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msecs_to_jiffies(300));
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if (!time_left) {
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/*
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* Clear GO and reset AUX channel
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* to cancel the current transaction.
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*/
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edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0);
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msm_edp_aux_ctrl(aux, 1);
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pr_err("%s: aux timeout,\n", __func__);
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ret = -ETIMEDOUT;
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goto unlock_exit;
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}
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DBG("completion");
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if (!aux->msg_err) {
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if (read) {
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ret = edp_msg_fifo_rx(aux, msg);
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if (ret < 0)
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goto unlock_exit;
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}
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msg->reply = native ?
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DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
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} else {
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/* Reply defer to retry */
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msg->reply = native ?
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DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
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/*
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* The sleep time in caller is not long enough to make sure
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* our H/W completes transactions. Add more defer time here.
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*/
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msleep(100);
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}
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/* Return requested size for success or retry */
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ret = msg->size;
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unlock_exit:
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mutex_unlock(&aux->msg_mutex);
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return ret;
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}
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void *msm_edp_aux_init(struct device *dev, void __iomem *regbase,
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struct drm_dp_aux **drm_aux)
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{
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struct edp_aux *aux = NULL;
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int ret;
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DBG("");
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aux = devm_kzalloc(dev, sizeof(*aux), GFP_KERNEL);
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if (!aux)
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return NULL;
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aux->base = regbase;
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mutex_init(&aux->msg_mutex);
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init_completion(&aux->msg_comp);
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aux->drm_aux.name = "msm_edp_aux";
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aux->drm_aux.dev = dev;
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aux->drm_aux.transfer = edp_aux_transfer;
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ret = drm_dp_aux_register(&aux->drm_aux);
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if (ret) {
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pr_err("%s: failed to register drm aux: %d\n", __func__, ret);
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mutex_destroy(&aux->msg_mutex);
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}
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if (drm_aux && aux)
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*drm_aux = &aux->drm_aux;
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return aux;
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}
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void msm_edp_aux_destroy(struct device *dev, struct edp_aux *aux)
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{
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if (aux) {
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drm_dp_aux_unregister(&aux->drm_aux);
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mutex_destroy(&aux->msg_mutex);
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}
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}
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irqreturn_t msm_edp_aux_irq(struct edp_aux *aux, u32 isr)
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{
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if (isr & EDP_INTR_TRANS_STATUS) {
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DBG("isr=%x", isr);
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edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0);
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if (isr & EDP_INTR_AUX_I2C_ERR)
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aux->msg_err = true;
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else
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aux->msg_err = false;
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complete(&aux->msg_comp);
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}
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return IRQ_HANDLED;
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}
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void msm_edp_aux_ctrl(struct edp_aux *aux, int enable)
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{
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u32 data;
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DBG("enable=%d", enable);
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data = edp_read(aux->base + REG_EDP_AUX_CTRL);
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if (enable) {
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data |= EDP_AUX_CTRL_RESET;
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edp_write(aux->base + REG_EDP_AUX_CTRL, data);
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/* Make sure full reset */
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wmb();
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usleep_range(500, 1000);
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data &= ~EDP_AUX_CTRL_RESET;
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data |= EDP_AUX_CTRL_ENABLE;
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edp_write(aux->base + REG_EDP_AUX_CTRL, data);
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} else {
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data &= ~EDP_AUX_CTRL_ENABLE;
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edp_write(aux->base + REG_EDP_AUX_CTRL, data);
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}
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}
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