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1922 lines
48 KiB
1922 lines
48 KiB
/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "clk: %s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/clock/qcom,camcc-atoll.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "common.h"
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#include "reset.h"
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#include "vdd-level-sdmmagpie.h"
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#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
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static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);
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enum {
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P_BI_TCXO,
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P_CAM_CC_PLL0_OUT_EVEN,
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P_CAM_CC_PLL1_OUT_EVEN,
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P_CAM_CC_PLL2_OUT_AUX2,
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P_CAM_CC_PLL2_OUT_EARLY,
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P_CAM_CC_PLL3_OUT_MAIN,
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P_CORE_BI_PLL_TEST_SE,
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};
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static const struct parent_map cam_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
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{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const cam_cc_parent_names_0[] = {
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"bi_tcxo",
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"cam_cc_pll1_out_even",
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"cam_cc_pll0_out_even",
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"core_bi_pll_test_se",
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};
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static const struct parent_map cam_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL2_OUT_AUX2, 1 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const cam_cc_parent_names_1[] = {
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"bi_tcxo",
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"cam_cc_pll2_out_aux2",
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"core_bi_pll_test_se",
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};
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static const struct parent_map cam_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL2_OUT_EARLY, 4 },
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{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
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{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const cam_cc_parent_names_2[] = {
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"bi_tcxo",
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"cam_cc_pll2_out_early",
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"cam_cc_pll3",
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"cam_cc_pll0_out_even",
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"core_bi_pll_test_se",
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};
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static const struct parent_map cam_cc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
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{ P_CAM_CC_PLL2_OUT_EARLY, 4 },
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{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
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{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const cam_cc_parent_names_3[] = {
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"bi_tcxo",
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"cam_cc_pll1_out_even",
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"cam_cc_pll2_out_early",
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"cam_cc_pll3",
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"cam_cc_pll0_out_even",
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"core_bi_pll_test_se",
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};
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static const struct parent_map cam_cc_parent_map_4[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
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{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const cam_cc_parent_names_4[] = {
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"bi_tcxo",
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"cam_cc_pll3",
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"cam_cc_pll0_out_even",
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"core_bi_pll_test_se",
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};
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static const struct parent_map cam_cc_parent_map_5[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const cam_cc_parent_names_5[] = {
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"bi_tcxo",
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"cam_cc_pll0_out_even",
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"core_bi_pll_test_se",
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};
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static const struct parent_map cam_cc_parent_map_6[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
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{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
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{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const cam_cc_parent_names_6[] = {
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"bi_tcxo",
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"cam_cc_pll1_out_even",
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"cam_cc_pll3",
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"cam_cc_pll0_out_even",
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"core_bi_pll_test_se",
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};
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static struct pll_vco agera_vco[] = {
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{ 600000000, 3300000000, 0 },
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{ 600000000, 2000000000, 1 },
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};
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static struct pll_vco fabia_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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/* 600MHz configuration */
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static const struct alpha_pll_config cam_cc_pll0_config = {
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.l = 0x1F,
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.frac = 0x4000,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00004805,
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};
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static struct clk_alpha_pll cam_cc_pll0 = {
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.offset = 0x0,
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.vco_table = fabia_vco,
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.num_vco = ARRAY_SIZE(fabia_vco),
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.type = FABIA_PLL,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "cam_cc_pll0",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_fabia_pll_ops,
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.vdd_class = &vdd_mx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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},
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},
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};
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static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
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{ 0x0, 1 },
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{ }
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
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.offset = 0x0,
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.post_div_shift = 8,
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.post_div_table = post_div_table_cam_cc_pll0_out_even,
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.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
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.width = 4,
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.type = FABIA_PLL,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "cam_cc_pll0_out_even",
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.parent_names = (const char *[]){ "cam_cc_pll0" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_generic_pll_postdiv_ops,
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},
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};
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/* 860MHz configuration */
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static const struct alpha_pll_config cam_cc_pll1_config = {
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.l = 0x2A,
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.frac = 0x1555,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00004805,
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};
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static struct clk_alpha_pll cam_cc_pll1 = {
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.offset = 0x1000,
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.vco_table = fabia_vco,
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.num_vco = ARRAY_SIZE(fabia_vco),
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.type = FABIA_PLL,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "cam_cc_pll1",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_fabia_pll_ops,
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.vdd_class = &vdd_mx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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},
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},
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};
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static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
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{ 0x0, 1 },
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{ }
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
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.offset = 0x1000,
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.post_div_shift = 8,
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.post_div_table = post_div_table_cam_cc_pll1_out_even,
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.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
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.width = 4,
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.type = FABIA_PLL,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "cam_cc_pll1_out_even",
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.parent_names = (const char *[]){ "cam_cc_pll1" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_generic_pll_postdiv_ops,
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},
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};
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/* 1920MHz configuration */
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static const struct alpha_pll_config cam_cc_pll2_config = {
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.l = 0x64,
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.post_div_val = 0x3 << 8,
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.post_div_mask = 0x3 << 8,
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.aux_output_mask = BIT(1),
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.main_output_mask = BIT(0),
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.early_output_mask = BIT(3),
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.config_ctl_hi_val = 0x400003d2,
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.config_ctl_val = 0x20000800,
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};
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static struct clk_alpha_pll cam_cc_pll2 = {
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.offset = 0x2000,
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.vco_table = agera_vco,
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.num_vco = ARRAY_SIZE(agera_vco),
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.type = AGERA_PLL,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "cam_cc_pll2",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_agera_pll_ops,
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.vdd_class = &vdd_mx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 1200000000,
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[VDD_LOWER] = 1800000000,
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[VDD_LOW] = 2400000000,
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[VDD_NOMINAL] = 3000000000,
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[VDD_HIGH] = 3300000000},
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},
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},
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};
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static struct clk_fixed_factor cam_cc_pll2_out_early = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data){
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.name = "cam_cc_pll2_out_early",
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.parent_names = (const char *[]){ "cam_cc_pll2" },
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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},
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};
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static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux2[] = {
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{ 0x1, 2 },
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{ }
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux2 = {
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.offset = 0x2000,
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.post_div_shift = 8,
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.post_div_table = post_div_table_cam_cc_pll2_out_aux2,
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.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux2),
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.width = 2,
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.type = AGERA_PLL,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "cam_cc_pll2_out_aux2",
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.parent_names = (const char *[]){ "cam_cc_pll2" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_ops,
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},
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};
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/* 1080MHz configuration */
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static const struct alpha_pll_config cam_cc_pll3_config = {
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.l = 0x38,
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.frac = 0x4000,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00004805,
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};
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static struct clk_alpha_pll cam_cc_pll3 = {
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.offset = 0x3000,
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.vco_table = fabia_vco,
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.num_vco = ARRAY_SIZE(fabia_vco),
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.type = FABIA_PLL,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "cam_cc_pll3",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_fabia_pll_ops,
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.vdd_class = &vdd_mx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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},
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},
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};
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static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
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F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
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F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
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F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
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F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 cam_cc_bps_clk_src = {
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.cmd_rcgr = 0x6010,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = cam_cc_parent_map_2,
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.freq_tbl = ftbl_cam_cc_bps_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "cam_cc_bps_clk_src",
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.parent_names = cam_cc_parent_names_2,
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.num_parents = 5,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 200000000,
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[VDD_LOW] = 360000000,
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[VDD_LOW_L1] = 432000000,
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[VDD_NOMINAL] = 480000000,
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[VDD_HIGH] = 600000000},
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},
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};
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static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
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F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
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F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
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{ }
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};
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static struct clk_rcg2 cam_cc_cci_0_clk_src = {
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.cmd_rcgr = 0xb0d8,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_cc_parent_map_5,
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.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "cam_cc_cci_0_clk_src",
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.parent_names = cam_cc_parent_names_5,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 37500000,
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[VDD_LOW] = 50000000,
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[VDD_NOMINAL] = 100000000},
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},
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};
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static struct clk_rcg2 cam_cc_cci_1_clk_src = {
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.cmd_rcgr = 0xb14c,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_cc_parent_map_5,
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.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "cam_cc_cci_1_clk_src",
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.parent_names = cam_cc_parent_names_5,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 37500000,
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[VDD_LOW] = 50000000,
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[VDD_NOMINAL] = 100000000},
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},
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};
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static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
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F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0),
|
|
F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
|
|
.cmd_rcgr = 0x9064,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_3,
|
|
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_cphy_rx_clk_src",
|
|
.parent_names = cam_cc_parent_names_3,
|
|
.num_parents = 6,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 150000000,
|
|
[VDD_LOW] = 270000000,
|
|
[VDD_LOW_L1] = 360000000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
|
|
.cmd_rcgr = 0x5004,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_csi0phytimer_clk_src",
|
|
.parent_names = cam_cc_parent_names_0,
|
|
.num_parents = 4,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 300000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
|
|
.cmd_rcgr = 0x5028,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_csi1phytimer_clk_src",
|
|
.parent_names = cam_cc_parent_names_0,
|
|
.num_parents = 4,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 300000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
|
|
.cmd_rcgr = 0x504c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_csi2phytimer_clk_src",
|
|
.parent_names = cam_cc_parent_names_0,
|
|
.num_parents = 4,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 300000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
|
|
.cmd_rcgr = 0x5070,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_csi3phytimer_clk_src",
|
|
.parent_names = cam_cc_parent_names_0,
|
|
.num_parents = 4,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 300000000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
|
|
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
|
|
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
|
|
F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
|
|
.cmd_rcgr = 0x603c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_fast_ahb_clk_src",
|
|
.parent_names = cam_cc_parent_names_0,
|
|
.num_parents = 4,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 100000000,
|
|
[VDD_LOW] = 200000000,
|
|
[VDD_LOW_L1] = 300000000,
|
|
[VDD_NOMINAL] = 404000000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
|
|
F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
|
|
F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
|
|
F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
|
|
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_icp_clk_src = {
|
|
.cmd_rcgr = 0xb088,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_2,
|
|
.freq_tbl = ftbl_cam_cc_icp_clk_src,
|
|
.enable_safe_config = true,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_icp_clk_src",
|
|
.parent_names = cam_cc_parent_names_2,
|
|
.num_parents = 5,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 240000000,
|
|
[VDD_LOW] = 360000000,
|
|
[VDD_LOW_L1] = 432000000,
|
|
[VDD_NOMINAL] = 480000000,
|
|
[VDD_HIGH] = 600000000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
|
|
F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
|
|
F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
|
|
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_ife_0_clk_src = {
|
|
.cmd_rcgr = 0x9010,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_4,
|
|
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
|
|
.enable_safe_config = true,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_0_clk_src",
|
|
.parent_names = cam_cc_parent_names_4,
|
|
.num_parents = 4,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 240000000,
|
|
[VDD_LOW] = 360000000,
|
|
[VDD_LOW_L1] = 432000000,
|
|
[VDD_NOMINAL] = 600000000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
|
|
F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0),
|
|
F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
|
|
F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
|
|
.cmd_rcgr = 0x903c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_3,
|
|
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
|
|
.enable_safe_config = true,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_0_csid_clk_src",
|
|
.parent_names = cam_cc_parent_names_3,
|
|
.num_parents = 6,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 150000000,
|
|
[VDD_LOW] = 270000000,
|
|
[VDD_LOW_L1] = 360000000,
|
|
[VDD_NOMINAL] = 480000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_ife_1_clk_src = {
|
|
.cmd_rcgr = 0xa010,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_4,
|
|
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
|
|
.enable_safe_config = true,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_1_clk_src",
|
|
.parent_names = cam_cc_parent_names_4,
|
|
.num_parents = 4,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 240000000,
|
|
[VDD_LOW] = 360000000,
|
|
[VDD_LOW_L1] = 432000000,
|
|
[VDD_NOMINAL] = 600000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
|
|
.cmd_rcgr = 0xa034,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_3,
|
|
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
|
|
.enable_safe_config = true,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_1_csid_clk_src",
|
|
.parent_names = cam_cc_parent_names_3,
|
|
.num_parents = 6,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 150000000,
|
|
[VDD_LOW] = 270000000,
|
|
[VDD_LOW_L1] = 360000000,
|
|
[VDD_NOMINAL] = 480000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
|
|
.cmd_rcgr = 0xb004,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_4,
|
|
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_lite_clk_src",
|
|
.parent_names = cam_cc_parent_names_4,
|
|
.num_parents = 4,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 240000000,
|
|
[VDD_LOW] = 360000000,
|
|
[VDD_LOW_L1] = 432000000,
|
|
[VDD_NOMINAL] = 600000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
|
|
.cmd_rcgr = 0xb024,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_3,
|
|
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
|
|
.enable_safe_config = true,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_lite_csid_clk_src",
|
|
.parent_names = cam_cc_parent_names_3,
|
|
.num_parents = 6,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 150000000,
|
|
[VDD_LOW] = 270000000,
|
|
[VDD_LOW_L1] = 360000000,
|
|
[VDD_NOMINAL] = 480000000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
|
|
F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
|
|
F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
|
|
F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0),
|
|
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
|
|
.cmd_rcgr = 0x7010,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_2,
|
|
.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
|
|
.enable_safe_config = true,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ipe_0_clk_src",
|
|
.parent_names = cam_cc_parent_names_2,
|
|
.num_parents = 5,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 240000000,
|
|
[VDD_LOW] = 360000000,
|
|
[VDD_LOW_L1] = 432000000,
|
|
[VDD_NOMINAL] = 540000000,
|
|
[VDD_HIGH] = 600000000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0),
|
|
F(133333333, P_CAM_CC_PLL0_OUT_EVEN, 4.5, 0, 0),
|
|
F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0),
|
|
F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0),
|
|
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_jpeg_clk_src = {
|
|
.cmd_rcgr = 0xb04c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_2,
|
|
.freq_tbl = ftbl_cam_cc_jpeg_clk_src,
|
|
.enable_safe_config = true,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_jpeg_clk_src",
|
|
.parent_names = cam_cc_parent_names_2,
|
|
.num_parents = 5,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 66666667,
|
|
[VDD_LOW] = 133333333,
|
|
[VDD_LOW_L1] = 216000000,
|
|
[VDD_NOMINAL] = 320000000,
|
|
[VDD_HIGH] = 600000000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
|
|
F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0),
|
|
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
|
|
F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_lrme_clk_src = {
|
|
.cmd_rcgr = 0xb0f8,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_6,
|
|
.freq_tbl = ftbl_cam_cc_lrme_clk_src,
|
|
.enable_safe_config = true,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_lrme_clk_src",
|
|
.parent_names = cam_cc_parent_names_6,
|
|
.num_parents = 5,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 200000000,
|
|
[VDD_LOW] = 216000000,
|
|
[VDD_LOW_L1] = 300000000,
|
|
[VDD_NOMINAL] = 404000000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(24000000, P_CAM_CC_PLL2_OUT_AUX2, 10, 1, 2),
|
|
F(64000000, P_CAM_CC_PLL2_OUT_AUX2, 7.5, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
|
|
.cmd_rcgr = 0x4004,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_1,
|
|
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_mclk0_clk_src",
|
|
.parent_names = cam_cc_parent_names_1,
|
|
.num_parents = 3,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 64000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
|
|
.cmd_rcgr = 0x4024,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_1,
|
|
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_mclk1_clk_src",
|
|
.parent_names = cam_cc_parent_names_1,
|
|
.num_parents = 3,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 64000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
|
|
.cmd_rcgr = 0x4044,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_1,
|
|
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_mclk2_clk_src",
|
|
.parent_names = cam_cc_parent_names_1,
|
|
.num_parents = 3,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 64000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
|
|
.cmd_rcgr = 0x4064,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_1,
|
|
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_mclk3_clk_src",
|
|
.parent_names = cam_cc_parent_names_1,
|
|
.num_parents = 3,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 64000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_mclk4_clk_src = {
|
|
.cmd_rcgr = 0x4084,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_1,
|
|
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_mclk4_clk_src",
|
|
.parent_names = cam_cc_parent_names_1,
|
|
.num_parents = 3,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 64000000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
|
|
.cmd_rcgr = 0x6058,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
|
|
.enable_safe_config = true,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_slow_ahb_clk_src",
|
|
.parent_names = cam_cc_parent_names_0,
|
|
.num_parents = 4,
|
|
.ops = &clk_rcg2_ops,
|
|
.vdd_class = &vdd_cx,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOWER] = 80000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_bps_ahb_clk = {
|
|
.halt_reg = 0x6070,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x6070,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_bps_ahb_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_slow_ahb_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_bps_areg_clk = {
|
|
.halt_reg = 0x6054,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x6054,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_bps_areg_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_fast_ahb_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_bps_axi_clk = {
|
|
.halt_reg = 0x6038,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x6038,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_bps_axi_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_bps_clk = {
|
|
.halt_reg = 0x6028,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x6028,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_bps_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_bps_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_camnoc_axi_clk = {
|
|
.halt_reg = 0xb124,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb124,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_camnoc_axi_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cci_0_clk = {
|
|
.halt_reg = 0xb0f0,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb0f0,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_cci_0_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_cci_0_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cci_1_clk = {
|
|
.halt_reg = 0xb164,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb164,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_cci_1_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_cci_1_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_core_ahb_clk = {
|
|
.halt_reg = 0xb144,
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
.clkr = {
|
|
.enable_reg = 0xb144,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_core_ahb_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_slow_ahb_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cpas_ahb_clk = {
|
|
.halt_reg = 0xb11c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb11c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_cpas_ahb_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_slow_ahb_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csi0phytimer_clk = {
|
|
.halt_reg = 0x501c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x501c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_csi0phytimer_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_csi0phytimer_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csi1phytimer_clk = {
|
|
.halt_reg = 0x5040,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x5040,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_csi1phytimer_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_csi1phytimer_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csi2phytimer_clk = {
|
|
.halt_reg = 0x5064,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x5064,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_csi2phytimer_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_csi2phytimer_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csi3phytimer_clk = {
|
|
.halt_reg = 0x5088,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x5088,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_csi3phytimer_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_csi3phytimer_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csiphy0_clk = {
|
|
.halt_reg = 0x5020,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x5020,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_csiphy0_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_cphy_rx_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csiphy1_clk = {
|
|
.halt_reg = 0x5044,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x5044,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_csiphy1_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_cphy_rx_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csiphy2_clk = {
|
|
.halt_reg = 0x5068,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x5068,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_csiphy2_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_cphy_rx_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csiphy3_clk = {
|
|
.halt_reg = 0x508c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x508c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_csiphy3_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_cphy_rx_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_icp_clk = {
|
|
.halt_reg = 0xb0a0,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb0a0,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_icp_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_icp_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_icp_ts_clk = {
|
|
.halt_reg = 0xb080,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb080,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_icp_ts_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_0_axi_clk = {
|
|
.halt_reg = 0x9080,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x9080,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_0_axi_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_0_clk = {
|
|
.halt_reg = 0x9028,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x9028,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_0_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_ife_0_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
|
|
.halt_reg = 0x907c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x907c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_0_cphy_rx_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_cphy_rx_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_0_csid_clk = {
|
|
.halt_reg = 0x9054,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x9054,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_0_csid_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_ife_0_csid_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_0_dsp_clk = {
|
|
.halt_reg = 0x9038,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x9038,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_0_dsp_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_ife_0_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_1_axi_clk = {
|
|
.halt_reg = 0xa058,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa058,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_1_axi_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_1_clk = {
|
|
.halt_reg = 0xa028,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa028,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_1_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_ife_1_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
|
|
.halt_reg = 0xa054,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa054,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_1_cphy_rx_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_cphy_rx_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_1_csid_clk = {
|
|
.halt_reg = 0xa04c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa04c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_1_csid_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_ife_1_csid_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_1_dsp_clk = {
|
|
.halt_reg = 0xa030,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa030,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_1_dsp_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_ife_1_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_lite_clk = {
|
|
.halt_reg = 0xb01c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb01c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_lite_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_ife_lite_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
|
|
.halt_reg = 0xb044,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb044,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_lite_cphy_rx_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_cphy_rx_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_lite_csid_clk = {
|
|
.halt_reg = 0xb03c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb03c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ife_lite_csid_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_ife_lite_csid_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ipe_0_ahb_clk = {
|
|
.halt_reg = 0x7040,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x7040,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ipe_0_ahb_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_slow_ahb_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ipe_0_areg_clk = {
|
|
.halt_reg = 0x703c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x703c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ipe_0_areg_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_fast_ahb_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ipe_0_axi_clk = {
|
|
.halt_reg = 0x7038,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x7038,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ipe_0_axi_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ipe_0_clk = {
|
|
.halt_reg = 0x7028,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x7028,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_ipe_0_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_ipe_0_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_jpeg_clk = {
|
|
.halt_reg = 0xb064,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb064,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_jpeg_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_jpeg_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_lrme_clk = {
|
|
.halt_reg = 0xb110,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb110,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_lrme_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_lrme_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_mclk0_clk = {
|
|
.halt_reg = 0x401c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x401c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_mclk0_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_mclk0_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_mclk1_clk = {
|
|
.halt_reg = 0x403c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x403c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_mclk1_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_mclk1_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_mclk2_clk = {
|
|
.halt_reg = 0x405c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x405c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_mclk2_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_mclk2_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_mclk3_clk = {
|
|
.halt_reg = 0x407c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x407c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_mclk3_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_mclk3_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_mclk4_clk = {
|
|
.halt_reg = 0x409c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x409c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_mclk4_clk",
|
|
.parent_names = (const char *[]){
|
|
"cam_cc_mclk4_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_soc_ahb_clk = {
|
|
.halt_reg = 0xb140,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb140,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_soc_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_sys_tmr_clk = {
|
|
.halt_reg = 0xb0a8,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xb0a8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "cam_cc_sys_tmr_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct clk_hw *cam_cc_atoll_hws[] = {
|
|
[CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw,
|
|
};
|
|
|
|
static struct clk_regmap *cam_cc_atoll_clocks[] = {
|
|
[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
|
|
[CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
|
|
[CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
|
|
[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
|
|
[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
|
|
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
|
|
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
|
|
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
|
|
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
|
|
[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
|
|
[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
|
|
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
|
|
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
|
|
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
|
|
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
|
|
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
|
|
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
|
|
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
|
|
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
|
|
[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
|
|
[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
|
|
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
|
|
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
|
|
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
|
|
[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
|
|
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
|
|
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
|
|
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
|
|
[CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr,
|
|
[CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
|
|
[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
|
|
[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
|
|
[CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
|
|
[CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
|
|
[CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
|
|
[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
|
|
[CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
|
|
[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
|
|
[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
|
|
[CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
|
|
[CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
|
|
[CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
|
|
[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
|
|
[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
|
|
[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
|
|
[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
|
|
[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
|
|
[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
|
|
[CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
|
|
[CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
|
|
[CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
|
|
[CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
|
|
[CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
|
|
[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
|
|
[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
|
|
[CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr,
|
|
[CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr,
|
|
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
|
|
[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
|
|
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
|
|
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
|
|
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
|
|
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
|
|
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
|
|
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
|
|
[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
|
|
[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
|
|
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
|
|
[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
|
|
[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
|
|
[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
|
|
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
|
|
[CAM_CC_PLL2_OUT_AUX2] = &cam_cc_pll2_out_aux2.clkr,
|
|
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
|
|
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
|
|
[CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr,
|
|
[CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr,
|
|
};
|
|
|
|
static const struct regmap_config cam_cc_atoll_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0xd028,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static const struct qcom_cc_desc cam_cc_atoll_desc = {
|
|
.config = &cam_cc_atoll_regmap_config,
|
|
.clks = cam_cc_atoll_clocks,
|
|
.num_clks = ARRAY_SIZE(cam_cc_atoll_clocks),
|
|
.hwclks = cam_cc_atoll_hws,
|
|
.num_hwclks = ARRAY_SIZE(cam_cc_atoll_hws),
|
|
};
|
|
|
|
static const struct of_device_id cam_cc_atoll_match_table[] = {
|
|
{ .compatible = "qcom,atoll-camcc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, cam_cc_atoll_match_table);
|
|
|
|
static int cam_cc_atoll_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
int ret;
|
|
|
|
vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
|
|
if (IS_ERR(vdd_cx.regulator[0])) {
|
|
if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER)
|
|
dev_err(&pdev->dev,
|
|
"Unable to get vdd_cx regulator\n");
|
|
return PTR_ERR(vdd_cx.regulator[0]);
|
|
}
|
|
|
|
vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");
|
|
if (IS_ERR(vdd_mx.regulator[0])) {
|
|
if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER)
|
|
dev_err(&pdev->dev,
|
|
"Unable to get vdd_mx regulator\n");
|
|
return PTR_ERR(vdd_mx.regulator[0]);
|
|
}
|
|
|
|
regmap = qcom_cc_map(pdev, &cam_cc_atoll_desc);
|
|
if (IS_ERR(regmap)) {
|
|
pr_err("Failed to map the cam_cc registers\n");
|
|
return PTR_ERR(regmap);
|
|
}
|
|
|
|
clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
|
|
clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
|
|
clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
|
|
clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
|
|
|
|
ret = qcom_cc_really_probe(pdev, &cam_cc_atoll_desc, regmap);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register Camera CC clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "Registered Camera CC clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver cam_cc_atoll_driver = {
|
|
.probe = cam_cc_atoll_probe,
|
|
.driver = {
|
|
.name = "atoll-camcc",
|
|
.of_match_table = cam_cc_atoll_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init cam_cc_atoll_init(void)
|
|
{
|
|
return platform_driver_register(&cam_cc_atoll_driver);
|
|
}
|
|
subsys_initcall(cam_cc_atoll_init);
|
|
|
|
static void __exit cam_cc_atoll_exit(void)
|
|
{
|
|
platform_driver_unregister(&cam_cc_atoll_driver);
|
|
}
|
|
module_exit(cam_cc_atoll_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI CAM_CC atoll Driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:cam_cc-atoll");
|
|
|