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366 lines
8.3 KiB
366 lines
8.3 KiB
// SPDX-License-Identifier: GPL-2.0
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "brcm,bcm7358";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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mips-hpt-frequency = <375000000>;
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cpu@0 {
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compatible = "brcm,bmips3300";
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device_type = "cpu";
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reg = <0>;
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};
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};
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aliases {
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uart0 = &uart0;
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};
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cpu_intc: interrupt-controller {
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#address-cells = <0>;
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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clocks {
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uart_clk: uart_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <81000000>;
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};
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upg_clk: upg_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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};
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rdb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x10000000 0x01000000>;
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periph_intc: interrupt-controller@411400 {
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compatible = "brcm,bcm7038-l1-intc";
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reg = <0x411400 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>;
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};
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sun_l2_intc: interrupt-controller@403000 {
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compatible = "brcm,l2-intc";
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reg = <0x403000 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <48>;
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};
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gisb-arb@400000 {
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compatible = "brcm,bcm7400-gisb-arb";
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reg = <0x400000 0xdc>;
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native-endian;
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interrupt-parent = <&sun_l2_intc>;
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interrupts = <0>, <2>;
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brcm,gisb-arb-master-mask = <0x2f3>;
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brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
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"rdc_0", "raaga_0",
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"avd_0", "jtag_0";
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};
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upg_irq0_intc: interrupt-controller@406600 {
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compatible = "brcm,bcm7120-l2-intc";
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reg = <0x406600 0x8>;
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brcm,int-map-mask = <0x44>, <0x7000000>;
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brcm,int-fwd-mask = <0x70000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <56>, <54>;
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interrupt-names = "upg_main", "upg_bsc";
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};
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upg_aon_irq0_intc: interrupt-controller@408b80 {
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compatible = "brcm,bcm7120-l2-intc";
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reg = <0x408b80 0x8>;
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brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
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brcm,int-fwd-mask = <0>;
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brcm,irq-can-wake;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <57>, <55>, <59>;
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interrupt-names = "upg_main_aon", "upg_bsc_aon",
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"upg_spi";
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};
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sun_top_ctrl: syscon@404000 {
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compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
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reg = <0x404000 0x51c>;
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native-endian;
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};
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reboot {
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compatible = "brcm,brcmstb-reboot";
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syscon = <&sun_top_ctrl 0x304 0x308>;
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};
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uart0: serial@406800 {
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compatible = "ns16550a";
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reg = <0x406800 0x20>;
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reg-io-width = <0x4>;
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reg-shift = <0x2>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <61>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart1: serial@406840 {
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compatible = "ns16550a";
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reg = <0x406840 0x20>;
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reg-io-width = <0x4>;
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reg-shift = <0x2>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <62>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart2: serial@406880 {
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compatible = "ns16550a";
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reg = <0x406880 0x20>;
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reg-io-width = <0x4>;
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reg-shift = <0x2>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <63>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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bsca: i2c@406200 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406200 0x58>;
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interrupts = <24>;
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interrupt-names = "upg_bsca";
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status = "disabled";
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};
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bscb: i2c@406280 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406280 0x58>;
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interrupts = <25>;
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interrupt-names = "upg_bscb";
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status = "disabled";
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};
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bscc: i2c@406300 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406300 0x58>;
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interrupts = <26>;
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interrupt-names = "upg_bscc";
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status = "disabled";
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};
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bscd: i2c@408980 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_aon_irq0_intc>;
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reg = <0x408980 0x58>;
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interrupts = <27>;
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interrupt-names = "upg_bscd";
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status = "disabled";
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};
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pwma: pwm@406400 {
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compatible = "brcm,bcm7038-pwm";
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reg = <0x406400 0x28>;
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#pwm-cells = <2>;
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clocks = <&upg_clk>;
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status = "disabled";
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};
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pwmb: pwm@406700 {
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compatible = "brcm,bcm7038-pwm";
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reg = <0x406700 0x28>;
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#pwm-cells = <2>;
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clocks = <&upg_clk>;
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status = "disabled";
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};
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aon_pm_l2_intc: interrupt-controller@408240 {
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compatible = "brcm,l2-intc";
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reg = <0x408240 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <50>;
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brcm,irq-can-wake;
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};
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upg_gio: gpio@406500 {
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compatible = "brcm,brcmstb-gpio";
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reg = <0x406500 0xa0>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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gpio-controller;
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interrupt-controller;
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interrupt-parent = <&upg_irq0_intc>;
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interrupts = <6>;
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brcm,gpio-bank-widths = <32 32 32 29 4>;
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};
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upg_gio_aon: gpio@408c00 {
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compatible = "brcm,brcmstb-gpio";
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reg = <0x408c00 0x60>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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gpio-controller;
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interrupt-controller;
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interrupt-parent = <&upg_aon_irq0_intc>;
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interrupts = <6>;
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interrupts-extended = <&upg_aon_irq0_intc 6>,
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<&aon_pm_l2_intc 5>;
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wakeup-source;
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brcm,gpio-bank-widths = <21 32 2>;
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};
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enet0: ethernet@430000 {
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phy-mode = "internal";
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phy-handle = <&phy1>;
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mac-address = [ 00 10 18 36 23 1a ];
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compatible = "brcm,genet-v2";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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reg = <0x430000 0x4c8c>;
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interrupts = <24>, <25>;
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interrupt-parent = <&periph_intc>;
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status = "disabled";
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mdio@e14 {
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compatible = "brcm,genet-mdio-v2";
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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reg = <0xe14 0x8>;
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phy1: ethernet-phy@1 {
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max-speed = <100>;
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reg = <0x1>;
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compatible = "brcm,40nm-ephy",
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"ethernet-phy-ieee802.3-c22";
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};
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};
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};
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ehci0: usb@480300 {
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compatible = "brcm,bcm7358-ehci", "generic-ehci";
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reg = <0x480300 0x100>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <65>;
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status = "disabled";
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};
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ohci0: usb@480400 {
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compatible = "brcm,bcm7358-ohci", "generic-ohci";
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reg = <0x480400 0x100>;
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native-endian;
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no-big-frame-no;
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interrupt-parent = <&periph_intc>;
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interrupts = <66>;
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status = "disabled";
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};
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hif_l2_intc: interrupt-controller@411000 {
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compatible = "brcm,l2-intc";
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reg = <0x411000 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <30>;
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};
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nand: nand@412800 {
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compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "nand";
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reg = <0x412800 0x400>;
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interrupt-parent = <&hif_l2_intc>;
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interrupts = <24>;
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status = "disabled";
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};
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spi_l2_intc: interrupt-controller@411d00 {
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compatible = "brcm,l2-intc";
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reg = <0x411d00 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <31>;
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};
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qspi: spi@413000 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-qspi";
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clocks = <&upg_clk>;
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reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
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reg-names = "cs_reg", "hif_mspi", "bspi";
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interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
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interrupt-parent = <&spi_l2_intc>;
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interrupt-names = "spi_lr_fullness_reached",
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"spi_lr_session_aborted",
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"spi_lr_impatient",
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"spi_lr_session_done",
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"spi_lr_overread",
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"mspi_done",
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"mspi_halted";
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status = "disabled";
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};
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mspi: spi@408a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-mspi";
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clocks = <&upg_clk>;
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reg = <0x408a00 0x180>;
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reg-names = "mspi";
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interrupts = <0x14>;
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interrupt-parent = <&upg_aon_irq0_intc>;
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interrupt-names = "mspi_done";
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status = "disabled";
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};
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};
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};
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