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279 lines
7.1 KiB
279 lines
7.1 KiB
/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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pil_gpu: qcom,kgsl-hyp {
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compatible = "qcom,pil-tz-generic";
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qcom,pas-id = <13>;
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qcom,firmware-name = "a610_zap";
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};
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msm_bus: qcom,kgsl-busmon{
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label = "kgsl-busmon";
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compatible = "qcom,kgsl-busmon";
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};
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gpu_bw_tbl: gpu-bw-tbl {
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compatible = "operating-points-v2";
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opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */
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opp-100 { opp-hz = /bits/ 64 < 762 >; }; /* 1.100 MHz */
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opp-200 { opp-hz = /bits/ 64 < 1525 >; }; /* 2.200 MHz */
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opp-300 { opp-hz = /bits/ 64 < 2288 >; }; /* 3.300 MHz */
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opp-451 { opp-hz = /bits/ 64 < 3440 >; }; /* 4.451 MHz */
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opp-547 { opp-hz = /bits/ 64 < 4173 >; }; /* 5.547 MHz */
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opp-681 { opp-hz = /bits/ 64 < 5195 >; }; /* 6.681 MHz */
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opp-768 { opp-hz = /bits/ 64 < 5859 >; }; /* 7.768 MHz */
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opp-1017 { opp-hz = /bits/ 64 < 7759 >; }; /* 8.1017 MHz */
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opp-1353 { opp-hz = /bits/ 64 < 10322 >; }; /* 9.1353 MHz */
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opp-1555 { opp-hz = /bits/ 64 < 11863 >; }; /* 10.1555 MHz */
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opp-1804 { opp-hz = /bits/ 64 < 13763 >; }; /* 11.1804 MHz */
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};
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gpubw: qcom,gpubw {
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compatible = "qcom,devbw";
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governor = "bw_vbif";
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qcom,src-dst-ports = <26 512>;
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operating-points-v2 = <&gpu_bw_tbl>;
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};
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msm_gpu: qcom,kgsl-3d0@5900000 {
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label = "kgsl-3d0";
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compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
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status = "ok";
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reg = <0x5900000 0x90000>,
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<0x5961000 0x800>,
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<0x1b40000 0x6fff>;
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reg-names = "kgsl_3d0_reg_memory", "cx_dbgc",
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"qfprom_memory";
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interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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qcom,id = <0>;
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qcom,chipid = <0x06010000>;
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qcom,initial-pwrlevel = <6>;
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qcom,idle-timeout = <80>;
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qcom,ubwc-mode = <1>;
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qcom,min-access-length = <64>;
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qcom,highest-bank-bit = <14>;
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/* size in bytes */
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qcom,snapshot-size = <1048576>;
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/* base addr, size */
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qcom,gpu-qdss-stm = <0xe1c0000 0x40000>;
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#cooling-cells = <2>;
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clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK>,
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<&clock_gpucc GPU_CC_CXO_CLK>,
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<&clock_gcc GCC_BIMC_GPU_AXI_CLK>,
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<&clock_gpucc GPU_CC_AHB_CLK>,
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<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&clock_gcc GCC_SYS_NOC_COMPUTE_SF_AXI_CLK>,
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<&clock_gpucc GPU_CC_CX_GMU_CLK>,
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<&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
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clock-names = "core_clk", "rbbmtimer_clk", "mem_clk",
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"iface_clk", "mem_iface_clk",
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"alt_mem_iface_clk", "gmu_clk",
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"smmu_vote";
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/* Bus Scale Settings */
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qcom,gpubw-dev = <&gpubw>;
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qcom,bus-control;
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qcom,msm-bus,name = "grp3d";
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qcom,bus-width = <32>;
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qcom,msm-bus,num-cases = <12>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<26 512 0 0>,
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<26 512 0 800000>, /* 1 bus=100 (LOW SVS) */
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<26 512 0 1600000>, /* 2 bus=200 (LOW SVS) */
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<26 512 0 2400000>, /* 3 bus=300 (LOW SVS) */
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<26 512 0 3608000>, /* 4 bus=451 (LOW SVS) */
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<26 512 0 4376000>, /* 5 bus=547 (LOW SVS) */
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<26 512 0 5448000>, /* 6 bus=681 (SVS) */
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<26 512 0 6144000>, /* 7 bus=768 (SVS) */
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<26 512 0 8136000>, /* 8 bus=1017 (SVS_L1) */
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<26 512 0 10824000>, /* 9 bus=1353 (NOM) */
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<26 512 0 12440000>, /* 10 bus=1555 (NOM) */
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<26 512 0 14432000>; /* 11 bus=1804 (TURBO) */
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/* GDSC regulator names */
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regulator-names = "vddcx", "vdd";
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/* GDSC oxili regulators */
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vddcx-supply = <&gpu_cx_gdsc>;
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vdd-supply = <&gpu_gx_gdsc>;
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/* CPU latency parameter */
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qcom,pm-qos-active-latency = <422>;
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qcom,pm-qos-wakeup-latency = <422>;
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/* Enable context aware freq. scaling */
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qcom,enable-ca-jump;
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/* Context aware jump busy penalty in us */
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qcom,ca-busy-penalty = <12000>;
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/* Context aware jump target power level */
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qcom,ca-target-pwrlevel = <5>;
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qcom,gpu-gaming-bin = <0x6018 0x80 7>;
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/* CX iPeak limit support */
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qcom,gpu-cx-ipeak = <&cx_ipeak_lm 5>;
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/* GPU Mempools */
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-allocate;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-allocate;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
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};
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/* Power levels */
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qcom,gpu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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/* TURBO_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <950000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <11>;
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};
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <900000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <9>;
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qcom,bus-max = <11>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <820000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <11>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <745000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <600000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <465000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <8>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <320000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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/* XO */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <0>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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};
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kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x59a0000 0x10000>;
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qcom,protect = <0xa0000 0x10000>;
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clocks = <&clock_gcc GCC_BIMC_GPU_AXI_CLK>,
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<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&clock_gcc GCC_SYS_NOC_COMPUTE_SF_AXI_CLK>,
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<&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
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clock-names = "mem_clk", "mem_iface_clk",
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"alt_mem_iface_clk", "smmu_vote";
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qcom,retention;
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qcom,hyp_secure_alloc;
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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label = "gfx3d_user";
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iommus = <&kgsl_smmu 0 1>;
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qcom,gpu-offset = <0xa8000>;
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};
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gfx3d_secure: gfx3d_secure {
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compatible = "qcom,smmu-kgsl-cb";
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label = "gfx3d_secure";
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iommus = <&kgsl_smmu 2 0>;
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};
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};
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};
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