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437 lines
12 KiB
437 lines
12 KiB
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/qcom,gcc-sm6150.h>
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#include <dt-bindings/msm/msm-bus-ids.h>
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&soc {
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/* Primary USB port related controller */
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0xa600000 0x100000>;
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reg-names = "core_base";
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iommus = <&apps_smmu 0x140 0x0>;
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qcom,smmu-s1-bypass;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"ss_phy_irq", "dm_hs_phy_irq";
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qcom,use-pdc-interrupts;
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USB3_GDSC-supply = <&usb30_prim_gdsc>;
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dpdm-supply = <&qusb_phy0>;
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clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
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<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"xo", "sleep_clk", "utmi_clk";
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resets = <&clock_gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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qcom,gsi-disable-io-coherency;
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qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
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qcom,pm-qos-latency = <61>;
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qcom,msm-bus,name = "usb0";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <3>;
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qcom,msm-bus,vectors-KBps =
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/* suspend vote */
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<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>,
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<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>,
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/* nominal vote */
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<MSM_BUS_MASTER_USB3
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MSM_BUS_SLAVE_EBI_CH0 1000000 2500000>,
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<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
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/* svs vote */
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<MSM_BUS_MASTER_USB3
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MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
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<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
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/* min vote */
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<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 1 1>,
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<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>;
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0xa600000 0xcd00>;
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interrupt-parent = <&intc>;
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interrupts = <0 133 0>;
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usb-phy = <&qusb_phy0>, <&usb_qmp_phy>;
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tx-fifo-resize;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3_lpm_capable;
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usb-core-id = <0>;
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maximum-speed = "super-speed";
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dr_mode = "otg";
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};
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qcom,usbbam@a704000 {
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compatible = "qcom,usb-bam-msm";
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reg = <0xa704000 0x17000>;
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interrupts = <0 132 0>;
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qcom,usb-bam-fifo-baseaddr = <0x146a6000>;
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qcom,usb-bam-num-pipes = <4>;
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qcom,disable-clk-gating;
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qcom,usb-bam-override-threshold = <0x4001>;
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qcom,usb-bam-max-mbps-highspeed = <400>;
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qcom,usb-bam-max-mbps-superspeed = <3600>;
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qcom,reset-bam-on-connect;
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qcom,pipe0 {
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label = "ssusb-qdss-in-0";
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qcom,usb-bam-mem-type = <2>;
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qcom,dir = <1>;
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qcom,pipe-num = <0>;
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qcom,peer-bam = <0>;
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qcom,peer-bam-physical-address = <0x6064000>;
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qcom,src-bam-pipe-index = <0>;
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qcom,dst-bam-pipe-index = <0>;
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qcom,data-fifo-offset = <0x0>;
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qcom,data-fifo-size = <0x1800>;
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qcom,descriptor-fifo-offset = <0x1800>;
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qcom,descriptor-fifo-size = <0x800>;
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};
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};
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};
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/* Primary USB port related High Speed PHY */
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qusb_phy0: qusb@88e2000 {
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compatible = "qcom,qusb2phy";
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reg = <0x88e2000 0x180>,
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<0x01fcb250 0x4>,
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<0x007801f8 0x4>,
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<0x01fcb3e4 0x4>;
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reg-names = "qusb_phy_base",
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"tcsr_clamp_dig_n_1p8",
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"tune2_efuse_addr",
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"tcsr_conn_box_spare_0";
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vdd-supply = <&pm6150_l4>;
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vdda18-supply = <&pm6150_l11>;
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vdda33-supply = <&pm6150_l17>;
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qcom,vdd-voltage-level = <0 925000 975000>;
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qcom,tune2-efuse-bit-pos = <25>;
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qcom,tune2-efuse-num-bits = <4>;
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qcom,qusb-phy-init-seq = <0xc8 0x80
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0xb3 0x84
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0x83 0x88
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0xc0 0x8c
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0x30 0x08
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0x79 0x0c
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0x21 0x10
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0x14 0x9c
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0x9f 0x1c
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0x00 0x18>;
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phy_type = "utmi";
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qcom,phy-clk-scheme = "cml";
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qcom,major-rev = <1>;
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/* USB2PHY gets clock directly from CXO pad
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* connected to differential pin cxo_core_in_1p8_vdda.
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*/
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clocks = <&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_AHB2PHY_WEST_CLK>;
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clock-names = "ref_clk_src", "cfg_ahb_clk";
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resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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};
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/* Primary USB port related QMP USB PHY */
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usb_qmp_phy: ssphy@88e6000 {
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compatible = "qcom,usb-ssphy-qmp-usb3-or-dp";
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reg = <0x88e6000 0x1000>,
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<0x01fcb244 0x4>;
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reg-names = "qmp_phy_base",
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"vls_clamp_reg";
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vdd-supply = <&pm6150_l4>;
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core-supply = <&pm6150_l11>;
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qcom,vdd-voltage-level = <0 925000 975000>;
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qcom,core-voltage-level = <0 1800000 1800000>;
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qcom,qmp-phy-init-seq =
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/* <reg_offset, value, delay> */
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<0xac 0x14 0x00
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0x34 0x08 0x00
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0x174 0x30 0x00
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0x3c 0x06 0x00
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0xb4 0x00 0x00
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0xb8 0x08 0x00
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0x70 0x0f 0x00
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0x19c 0x01 0x00
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0x178 0x00 0x00
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0xd0 0x82 0x00
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0xdc 0x55 0x00
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0xe0 0x55 0x00
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0xe4 0x03 0x00
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0x78 0x0b 0x00
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0x84 0x16 0x00
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0x90 0x28 0x00
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0x108 0x80 0x00
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0x10c 0x00 0x00
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0x184 0x0a 0x00
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0x4c 0x15 0x00
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0x50 0x34 0x00
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0x54 0x00 0x00
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0xc8 0x00 0x00
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0x18c 0x00 0x00
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0xcc 0x00 0x00
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0x128 0x00 0x00
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0x0c 0x0a 0x00
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0x10 0x01 0x00
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0x1c 0x31 0x00
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0x20 0x01 0x00
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0x14 0x00 0x00
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0x18 0x00 0x00
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0x24 0xde 0x00
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0x28 0x07 0x00
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0x48 0x0f 0x00
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0x194 0x06 0x00
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0x100 0x80 0x00
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0xa8 0x01 0x00
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0x430 0x0b 0x00
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0x830 0x0b 0x00
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0x444 0x00 0x00
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0x844 0x00 0x00
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0x43c 0x00 0x00
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0x83c 0x00 0x00
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0x440 0x00 0x00
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0x840 0x00 0x00
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0x408 0x0a 0x00
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0x808 0x0a 0x00
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0x414 0x06 0x00
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0x814 0x06 0x00
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0x434 0x75 0x00
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0x834 0x75 0x00
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0x4d4 0x02 0x00
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0x8d4 0x02 0x00
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0x4d8 0x4e 0x00
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0x8d8 0x4e 0x00
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0x4dc 0x18 0x00
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0x8dc 0x18 0x00
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0x4f8 0x77 0x00
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0x8f8 0x77 0x00
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0x4fc 0x80 0x00
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0x8fc 0x80 0x00
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0x4c0 0x0a 0x00
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0x8c0 0x0a 0x00
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0x504 0x03 0x00
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0x904 0x03 0x00
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0x50c 0x16 0x00
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0x90c 0x16 0x00
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0x500 0x00 0x00
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0x900 0x00 0x00
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0x564 0x00 0x00
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0x964 0x00 0x00
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0x260 0x10 0x00
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0x660 0x10 0x00
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0x2a4 0x12 0x00
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0x6a4 0x12 0x00
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0x28c 0xc6 0x00
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0x68c 0xc6 0x00
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0x244 0x00 0x00
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0x644 0x00 0x00
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0x248 0x00 0x00
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0x648 0x00 0x00
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0xc0c 0x9f 0x00
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0xc24 0x17 0x00
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0xc28 0x0f 0x00
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0xcc8 0x83 0x00
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0xcc4 0x02 0x00
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0xccc 0x09 0x00
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0xcd0 0xa2 0x00
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0xcd4 0x85 0x00
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0xc80 0xd1 0x00
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0xc84 0x1f 0x00
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0xc88 0x47 0x00
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0xcb8 0x75 0x00
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0xcbc 0x13 0x00
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0xcb0 0x86 0x00
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0xca0 0x04 0x00
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0xc8c 0x44 0x00
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0xc70 0xe7 0x00
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0xc74 0x03 0x00
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0xc78 0x40 0x00
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0xc7c 0x00 0x00
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0xdd8 0x88 0x00
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0xffffffff 0xffffffff 0x00>;
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qcom,qmp-phy-reg-offset =
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<0xd74 /* USB3_PHY_PCS_STATUS */
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0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */
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0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */
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0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */
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0xc00 /* USB3_PHY_SW_RESET */
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0xc08 /* USB3_PHY_START */
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0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */
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clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
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<&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
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<&clock_gcc GCC_AHB2PHY_WEST_CLK>;
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clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
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"ref_clk", "com_aux_clk", "cfg_ahb_clk";
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resets = <&clock_gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
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<&clock_gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
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reset-names = "phy_reset", "phy_phy_reset";
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};
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usb_audio_qmi_dev {
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compatible = "qcom,usb-audio-qmi-dev";
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iommus = <&apps_smmu 0x172f 0x0>;
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qcom,usb-audio-stream-id = <0xf>;
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qcom,usb-audio-intr-num = <2>;
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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/* Secondary USB port related controller */
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usb1: hsusb@a800000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0xa800000 0x100000>;
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reg-names = "core_base";
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iommus = <&apps_smmu 0xE0 0x0>;
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qcom,smmu-s1-bypass;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <0 491 0>, <0 663 0>, <0 490 0>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"dm_hs_phy_irq";
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qcom,use-pdc-interrupts;
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USB3_GDSC-supply = <&usb20_sec_gdsc>;
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clocks = <&clock_gcc GCC_USB20_SEC_MASTER_CLK>,
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<&clock_gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>,
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<&clock_gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
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<&clock_gcc GCC_USB3_SEC_CLKREF_CLK>,
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<&clock_gcc GCC_USB20_SEC_SLEEP_CLK>,
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<&clock_gcc GCC_USB20_SEC_MOCK_UTMI_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"xo", "sleep_clk", "utmi_clk";
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resets = <&clock_gcc GCC_USB20_SEC_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <120000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
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qcom,charging-disabled;
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qcom,msm-bus,name = "usb1";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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/* svs vote */
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<MSM_BUS_MASTER_USB_HS MSM_BUS_SLAVE_EBI_CH0 0 0>,
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<MSM_BUS_MASTER_USB_HS
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MSM_BUS_SLAVE_EBI_CH0 60000 800000>;
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status = "disabled";
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dwc3@a800000 {
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compatible = "snps,dwc3";
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reg = <0xa800000 0xcd00>;
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interrupt-parent = <&intc>;
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interrupts = <0 664 0>;
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usb-phy = <&qusb_phy1>, <&usb_nop_phy>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3_lpm_capable;
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usb-core-id = <1>;
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maximum-speed = "high-speed";
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dr_mode = "otg";
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};
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};
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/* Secondary USB port related High Speed PHY */
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qusb_phy1: qusb@88e3000 {
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compatible = "qcom,qusb2phy";
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reg = <0x88e3000 0x180>,
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<0x01fcb3e4 0x4>;
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reg-names = "qusb_phy_base",
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"tcsr_conn_box_spare_0";
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vdd-supply = <&pm6150_l4>;
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vdda18-supply = <&pm6150_l11>;
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vdda33-supply = <&pm6150_l17>;
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qcom,vdd-voltage-level = <0 925000 975000>;
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qcom,qusb-phy-init-seq = <0xc8 0x80
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0xb3 0x84
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0x83 0x88
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0xc0 0x8c
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0x30 0x08
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0x79 0x0c
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0x21 0x10
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0x14 0x9c
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0x9f 0x1c
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0x00 0x18>;
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phy_type = "utmi";
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qcom,phy-clk-scheme = "cml";
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qcom,major-rev = <1>;
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qcom,hold-reset;
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/* USB2PHY gets clock directly from CXO pad
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* connected to differential pin cxo_core_in_1p8_vdda.
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*/
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clocks = <&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_AHB2PHY_WEST_CLK>;
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clock-names = "ref_clk_src", "cfg_ahb_clk";
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|
|
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resets = <&clock_gcc GCC_QUSB2PHY_SEC_BCR>;
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|
reset-names = "phy_reset";
|
|
};
|
|
|
|
};
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|