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952 lines
26 KiB
952 lines
26 KiB
/* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
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&soc {
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mdss_mdp: qcom,mdss_mdp@ae00000 {
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compatible = "qcom,sde-kms";
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reg = <0xae00000 0x84208>,
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<0xaeb0000 0x2008>,
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<0xaeac000 0x214>;
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reg-names = "mdp_phys",
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"vbif_phys",
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"regdma_phys";
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clocks =
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<&clock_gcc GCC_DISP_AHB_CLK>,
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<&clock_gcc GCC_DISP_HF_AXI_CLK>,
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<&clock_gcc GCC_DISP_SF_AXI_CLK>,
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<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
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<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
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<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>,
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<&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
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clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
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"iface_clk", "core_clk", "vsync_clk",
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"lut_clk", "rot_clk";
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clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>;
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clock-max-rate = <0 0 0 0 460000000 19200000 460000000
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460000000>;
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sde-vdd-supply = <&mdss_core_gdsc>;
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/* interrupt config */
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interrupts = <0 83 0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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iommus = <&apps_smmu 0x800 0x420>,
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<&apps_smmu 0x820 0x420>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <0>;
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/* hw blocks */
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qcom,sde-off = <0x1000>;
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qcom,sde-len = <0x45c>;
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qcom,sde-ctl-off = <0x2000 0x2200 0x2400
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0x2600 0x2800 0x2a00>;
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qcom,sde-ctl-size = <0x1e0>;
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qcom,sde-ctl-display-pref = "primary", "primary", "none",
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"none", "none";
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qcom,sde-mixer-off = <0x45000 0x46000 0x47000
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0x48000 0x49000 0x4a000>;
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qcom,sde-mixer-size = <0x320>;
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qcom,sde-mixer-display-pref = "primary", "primary", "none",
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"none", "none", "none";
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qcom,sde-dspp-top-off = <0x1300>;
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qcom,sde-dspp-top-size = <0x80>;
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qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
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qcom,sde-dspp-size = <0x1800>;
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qcom,sde-dest-scaler-top-off = <0x00061000>;
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qcom,sde-dest-scaler-top-size = <0x1c>;
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qcom,sde-dest-scaler-off = <0x800 0x1000>;
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qcom,sde-dest-scaler-size = <0x800>;
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qcom,sde-wb-off = <0x66000>;
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qcom,sde-wb-size = <0x2c8>;
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qcom,sde-wb-xin-id = <6>;
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qcom,sde-wb-id = <2>;
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qcom,sde-wb-clk-ctrl = <0x3b8 24>;
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qcom,sde-intf-off = <0x6b000 0x6b800
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0x6c000 0x6c800 0x6d000 0x6d800>;
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qcom,sde-intf-size = <0x280>;
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qcom,sde-intf-type = "dp", "dsi", "dsi", "dp", "dp", "dp";
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qcom,sde-pp-off = <0x71000 0x71800
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0x72000 0x72800 0x73000 0x73800>;
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qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>;
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qcom,sde-pp-size = <0xd4>;
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qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>;
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qcom,sde-merge-3d-off = <0x84000 0x84100 0x84200>;
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qcom,sde-merge-3d-size = <0x100>;
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qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0 0x0>;
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qcom,sde-cdm-off = <0x7a200>;
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qcom,sde-cdm-size = <0x224>;
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qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00
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0x82000 0x82400>;
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qcom,sde-dsc-size = <0x140>;
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qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0
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0x30e0 0x30e0 0x30e0>;
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qcom,sde-dither-version = <0x00010000>;
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qcom,sde-dither-size = <0x20>;
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qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
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"dma", "dma", "dma", "dma";
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qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
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0x25000 0x27000 0x29000 0x2b000>;
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qcom,sde-sspp-src-size = <0x1f0>;
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qcom,sde-sspp-xin-id = <0 4 8 12
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1 5 9 13>;
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qcom,sde-sspp-excl-rect = <1 1 1 1
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1 1 1 1>;
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qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
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qcom,sde-smart-dma-rev = "smart_dma_v2p5";
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qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>;
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qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
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0xb0 0xc8 0xe0 0xf8 0x110>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-sspp-clk-ctrl =
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<0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
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<0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
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qcom,sde-sspp-csc-off = <0x1a00>;
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qcom,sde-csc-type = "csc-10bit";
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qcom,sde-qseed-type = "qseedv3";
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qcom,sde-sspp-qseed-off = <0xa00>;
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qcom,sde-mixer-linewidth = <2560>;
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qcom,sde-sspp-linewidth = <4096>;
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qcom,sde-wb-linewidth = <4096>;
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qcom,sde-mixer-blendstages = <0xb>;
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qcom,sde-highest-bank-bit = <0x3>;
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qcom,sde-ubwc-version = <0x300>;
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qcom,sde-ubwc-bw-calc-version = <0x1>;
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qcom,sde-macrotile-mode = <0x1>;
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qcom,sde-panic-per-pipe;
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qcom,sde-has-cdp;
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qcom,sde-has-src-split;
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qcom,sde-pipe-order-version = <0x1>;
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qcom,sde-has-dim-layer;
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qcom,sde-has-idle-pc;
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qcom,sde-has-dest-scaler;
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qcom,sde-max-dest-scaler-input-linewidth = <2048>;
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qcom,sde-max-dest-scaler-output-linewidth = <2560>;
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qcom,sde-max-bw-low-kbps = <9600000>;
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qcom,sde-max-bw-high-kbps = <9600000>;
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qcom,sde-min-core-ib-kbps = <2400000>;
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qcom,sde-min-llcc-ib-kbps = <800000>;
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qcom,sde-min-dram-ib-kbps = <800000>;
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qcom,sde-dram-channels = <2>;
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qcom,sde-num-nrt-paths = <0>;
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qcom,sde-dspp-ad-version = <0x00040000>;
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qcom,sde-dspp-ad-off = <0x28000 0x27000>;
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qcom,sde-vbif-off = <0>;
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qcom,sde-vbif-size = <0x1040>;
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qcom,sde-vbif-id = <0>;
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qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
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qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
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qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
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qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
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qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000
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0x00000000>;
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qcom,sde-safe-lut-linear =
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<4 0xfff8>,
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<0 0xfff0>;
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qcom,sde-safe-lut-macrotile =
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<10 0xfe00>,
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<11 0xfc00>,
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<12 0xf800>,
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<0 0xf000>;
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qcom,sde-safe-lut-nrt =
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<0 0xffff>;
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qcom,sde-safe-lut-cwb =
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<0 0xffff>;
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qcom,sde-qos-lut-linear =
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<4 0x00000000 0x00000357>,
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<5 0x00000000 0x00003357>,
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<6 0x00000000 0x00023357>,
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<7 0x00000000 0x00223357>,
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<8 0x00000000 0x02223357>,
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<9 0x00000000 0x22223357>,
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<10 0x00000002 0x22223357>,
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<11 0x00000022 0x22223357>,
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<12 0x00000222 0x22223357>,
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<13 0x00002222 0x22223357>,
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<14 0x00012222 0x22223357>,
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<0 0x00112222 0x22223357>;
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qcom,sde-qos-lut-macrotile =
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<10 0x00000003 0x44556677>,
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<11 0x00000033 0x44556677>,
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<12 0x00000233 0x44556677>,
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<13 0x00002233 0x44556677>,
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<14 0x00012233 0x44556677>,
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<0 0x00112233 0x44556677>;
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qcom,sde-qos-lut-nrt =
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<0 0x00000000 0x00000000>;
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qcom,sde-qos-lut-cwb =
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<0 0x75300000 0x00000000>;
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qcom,sde-cdp-setting = <1 1>, <1 0>;
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qcom,sde-qos-cpu-mask = <0x3>;
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qcom,sde-qos-cpu-dma-latency = <300>;
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qcom,sde-reg-dma-off = <0>;
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qcom,sde-reg-dma-version = <0x00010001>;
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qcom,sde-reg-dma-trigger-off = <0x119c>;
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qcom,sde-secure-sid-mask = <0x4200801>;
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qcom,sde-sspp-vig-blocks {
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qcom,sde-vig-csc-off = <0x1a00>;
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qcom,sde-vig-qseed-off = <0xa00>;
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qcom,sde-vig-qseed-size = <0xa0>;
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qcom,sde-vig-gamut = <0x1d00 0x00050000>;
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qcom,sde-vig-igc = <0x1d00 0x00050000>;
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qcom,sde-vig-inverse-pma;
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};
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qcom,sde-sspp-dma-blocks {
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dgm@0 {
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qcom,sde-dma-igc = <0x400 0x00050000>;
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qcom,sde-dma-gc = <0x600 0x00050000>;
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qcom,sde-dma-inverse-pma;
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qcom,sde-dma-csc-off = <0x200>;
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};
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dgm@1 {
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qcom,sde-dma-igc = <0x1400 0x00050000>;
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qcom,sde-dma-gc = <0x600 0x00050000>;
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qcom,sde-dma-inverse-pma;
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qcom,sde-dma-csc-off = <0x1200>;
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};
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};
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qcom,sde-dspp-blocks {
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qcom,sde-dspp-igc = <0x0 0x00030001>;
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qcom,sde-dspp-hsic = <0x800 0x00010007>;
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qcom,sde-dspp-memcolor = <0x880 0x00010007>;
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qcom,sde-dspp-hist = <0x800 0x00010007>;
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qcom,sde-dspp-sixzone= <0x900 0x00010007>;
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qcom,sde-dspp-vlut = <0xa00 0x00010008>;
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qcom,sde-dspp-gamut = <0x1000 0x00040001>;
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qcom,sde-dspp-pcc = <0x1700 0x00040000>;
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qcom,sde-dspp-gc = <0x17c0 0x00010008>;
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};
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "sde-vdd";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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smmu_sde_sec: qcom,smmu_sde_sec_cb {
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compatible = "qcom,smmu_sde_sec";
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iommus = <&apps_smmu 0x801 0x420>,
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<&apps_smmu 0x821 0x420>;
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};
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/* data and reg bus scale settings */
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qcom,sde-data-bus {
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qcom,msm-bus,name = "mdss_sde_mnoc";
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<22 773 0 0>, <23 773 0 0>,
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<22 773 0 6400000>, <23 773 0 6400000>,
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<22 773 0 6400000>, <23 773 0 6400000>;
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};
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qcom,sde-llcc-bus {
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qcom,msm-bus,name = "mdss_sde_llcc";
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<132 770 0 0>,
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<132 770 0 6400000>,
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<132 770 0 6400000>;
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};
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qcom,sde-ebi-bus {
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qcom,msm-bus,name = "mdss_sde_ebi";
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<129 512 0 0>,
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<129 512 0 6400000>,
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<129 512 0 6400000>;
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};
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qcom,sde-reg-bus {
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qcom,msm-bus,name = "mdss_reg";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,active-only;
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qcom,msm-bus,vectors-KBps =
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<1 590 0 0>,
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<1 590 0 76800>,
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<1 590 0 150000>,
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<1 590 0 300000>;
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};
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};
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sde_rscc: qcom,sde_rscc@af20000 {
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cell-index = <0>;
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compatible = "qcom,sde-rsc";
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reg = <0xaf20000 0x1c44>,
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<0xaf30000 0x3fd4>;
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reg-names = "drv", "wrapper";
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qcom,sde-rsc-version = <2>;
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status = "disabled";
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vdd-supply = <&mdss_core_gdsc>;
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clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
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<&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
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<&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
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clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
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clock-rate = <0 0 0>;
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qcom,sde-dram-channels = <2>;
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mboxes = <&disp_rsc 0>;
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mbox-names = "disp_rsc";
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/* data and reg bus scale settings */
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qcom,sde-data-bus {
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qcom,msm-bus,name = "disp_rsc_mnoc";
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qcom,msm-bus,active-only;
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<20003 20515 0 0>, <20004 20515 0 0>,
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<20003 20515 0 6400000>, <20004 20515 0 6400000>,
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<20003 20515 0 6400000>, <20004 20515 0 6400000>;
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};
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qcom,sde-llcc-bus {
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qcom,msm-bus,name = "disp_rsc_llcc";
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qcom,msm-bus,active-only;
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<20001 20513 0 0>,
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<20001 20513 0 6400000>,
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<20001 20513 0 6400000>;
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};
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qcom,sde-ebi-bus {
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qcom,msm-bus,name = "disp_rsc_ebi";
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qcom,msm-bus,active-only;
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<20000 20512 0 0>,
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<20000 20512 0 6400000>,
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<20000 20512 0 6400000>;
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};
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "mmcx";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_rotator: qcom,mdss_rotator@ae00000 {
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compatible = "qcom,sde_rotator";
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reg = <0xae00000 0xac000>,
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<0xaeb8000 0x3000>;
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reg-names = "mdp_phys",
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"rot_vbif_phys";
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#list-cells = <1>;
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qcom,mdss-rot-mode = <1>;
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qcom,mdss-highest-bank-bit = <0x3>;
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/* Bus Scale Settings */
|
|
qcom,msm-bus,name = "mdss_rotator";
|
|
qcom,msm-bus,num-cases = <3>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<25 512 0 0>,
|
|
<25 512 0 6400000>,
|
|
<25 512 0 6400000>;
|
|
|
|
rot-vdd-supply = <&mdss_core_gdsc>;
|
|
qcom,supply-names = "rot-vdd";
|
|
|
|
clocks =
|
|
<&clock_gcc GCC_DISP_AHB_CLK>,
|
|
<&clock_gcc GCC_DISP_SF_AXI_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
|
|
clock-names = "gcc_iface", "gcc_bus",
|
|
"iface_clk", "rot_clk";
|
|
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <2 0>;
|
|
|
|
power-domains = <&mdss_mdp>;
|
|
|
|
/* Offline rotator QoS setting */
|
|
qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
|
|
qcom,mdss-rot-vbif-memtype = <3 3>;
|
|
qcom,mdss-rot-cdp-setting = <1 1>;
|
|
qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
|
|
qcom,mdss-rot-danger-lut = <0x0 0x0>;
|
|
qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
|
|
|
|
/* Inline rotator QoS Setting */
|
|
/* setting default register values for RD - qos/danger/safe */
|
|
qcom,mdss-inline-rot-qos-lut = <0x44556677 0x00112233
|
|
0x44556677 0x00112233>;
|
|
qcom,mdss-inline-rot-danger-lut = <0x0055aaff 0x0000ffff>;
|
|
qcom,mdss-inline-rot-safe-lut = <0x0000f000 0x0000ff00>;
|
|
|
|
qcom,mdss-default-ot-rd-limit = <32>;
|
|
qcom,mdss-default-ot-wr-limit = <32>;
|
|
|
|
qcom,mdss-sbuf-headroom = <20>;
|
|
|
|
cache-slice-names = "rotator";
|
|
cache-slices = <&llcc 4>;
|
|
|
|
/* reg bus scale settings */
|
|
rot_reg: qcom,rot-reg-bus {
|
|
qcom,msm-bus,name = "mdss_rot_reg";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,active-only;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<1 590 0 0>,
|
|
<1 590 0 76800>;
|
|
};
|
|
|
|
smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
|
|
compatible = "qcom,smmu_sde_rot_unsec";
|
|
iommus = <&apps_smmu 0x2040 0x0>;
|
|
};
|
|
|
|
smmu_rot_sec: qcom,smmu_rot_sec_cb {
|
|
compatible = "qcom,smmu_sde_rot_sec";
|
|
iommus = <&apps_smmu 0x2041 0x0>;
|
|
};
|
|
};
|
|
|
|
mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
|
|
compatible = "qcom,dsi-ctrl-hw-v2.3";
|
|
label = "dsi-ctrl-0";
|
|
cell-index = <0>;
|
|
reg = <0xae94000 0x400>,
|
|
<0xaf08000 0x4>;
|
|
reg-names = "dsi_ctrl", "disp_cc_base";
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <4 0>;
|
|
vdda-1p2-supply = <&pm8150c_l3>;
|
|
clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
|
<&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
|
<&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
|
|
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
|
"pixel_clk", "pixel_clk_rcg",
|
|
"esc_clk";
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1200000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <21800>;
|
|
qcom,supply-disable-load = <4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
|
|
compatible = "qcom,dsi-ctrl-hw-v2.3";
|
|
label = "dsi-ctrl-1";
|
|
cell-index = <1>;
|
|
reg = <0xae96000 0x400>,
|
|
<0xaf08000 0x4>;
|
|
reg-names = "dsi_ctrl", "disp_cc_base";
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <5 0>;
|
|
vdda-1p2-supply = <&pm8150c_l3>;
|
|
clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
|
<&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
|
|
<&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
|
|
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
|
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1200000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <21800>;
|
|
qcom,supply-disable-load = <4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {
|
|
compatible = "qcom,dsi-phy-v4.0";
|
|
label = "dsi-phy-0";
|
|
cell-index = <0>;
|
|
reg = <0xae94400 0x7c0>;
|
|
reg-names = "dsi_phy";
|
|
vdda-0p9-supply = <&pm8150_2_l5>;
|
|
qcom,platform-strength-ctrl = [55 03
|
|
55 03
|
|
55 03
|
|
55 03
|
|
55 00];
|
|
qcom,platform-lane-config = [00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 8a 8a];
|
|
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <880000>;
|
|
qcom,supply-enable-load = <36000>;
|
|
qcom,supply-disable-load = <32>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi_phy1: qcom,mdss_dsi_phy0@ae96400 {
|
|
compatible = "qcom,dsi-phy-v4.0";
|
|
label = "dsi-phy-1";
|
|
cell-index = <1>;
|
|
reg = <0xae96400 0x7c0>;
|
|
reg-names = "dsi_phy";
|
|
vdda-0p9-supply = <&pm8150_2_l5>;
|
|
qcom,platform-strength-ctrl = [55 03
|
|
55 03
|
|
55 03
|
|
55 03
|
|
55 00];
|
|
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
|
qcom,platform-lane-config = [00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 8a 8a];
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <880000>;
|
|
qcom,supply-enable-load = <36000>;
|
|
qcom,supply-disable-load = <32>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sde_dp_mst_sim: qcom,dp-mst-sim {
|
|
compatible = "qcom,dp-mst-sim";
|
|
};
|
|
|
|
sde_dp0: qcom,dp_display@0{
|
|
cell-index = <0>;
|
|
compatible = "qcom,dp-display";
|
|
qcom,intf-index = <0>;
|
|
qcom,phy-index = <0>;
|
|
|
|
qcom,bond-dual-ctrl = <1 0>;
|
|
qcom,bond-tri-ctrl = <2 0 1>;
|
|
|
|
reg = <0xae90000 0x0dc>,
|
|
<0xae90200 0x0c0>,
|
|
<0xae90400 0x508>,
|
|
<0xae90a00 0x094>,
|
|
<0x88eaa00 0x200>,
|
|
<0x88ea200 0x200>,
|
|
<0x88ea600 0x200>,
|
|
<0xaf02000 0x1a0>,
|
|
<0x780000 0x621c>,
|
|
<0x88ea040 0x10>,
|
|
<0x88e8000 0x20>,
|
|
<0xaee1000 0x034>,
|
|
<0xae91000 0x094>;
|
|
/* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */
|
|
reg-names = "dp_ahb", "dp_aux", "dp_link",
|
|
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
|
|
"dp_mmss_cc", "qfprom_physical", "dp_pll",
|
|
"usb3_dp_com", "hdcp_physical", "dp_p1";
|
|
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <12 0>;
|
|
|
|
clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
|
<&clock_rpmh RPMH_CXO_CLK>,
|
|
<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
|
|
<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
|
|
<&mdss_dp0_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
|
|
<&mdss_dp0_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>,
|
|
<&mdss_dp2_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
|
|
clock-names = "core_aux_clk", "core_usb_ref_clk_src",
|
|
"core_usb_ref_clk", "core_usb_pipe_clk",
|
|
"link_clk", "link_iface_clk",
|
|
"crypto_clk", "pixel_clk_rcg", "pixel_parent",
|
|
"pixel1_clk_rcg", "pixel1_parent",
|
|
"strm0_pixel_clk", "strm1_pixel_clk",
|
|
"bond_pixel_parent";
|
|
|
|
qcom,phy-version = <0x420>;
|
|
qcom,phy-mode = "dp";
|
|
qcom,aux-cfg0-settings = [20 00];
|
|
qcom,aux-cfg1-settings = [24 13];
|
|
qcom,aux-cfg2-settings = [28 24];
|
|
qcom,aux-cfg3-settings = [2c 00];
|
|
qcom,aux-cfg4-settings = [30 0a];
|
|
qcom,aux-cfg5-settings = [34 26];
|
|
qcom,aux-cfg6-settings = [38 0a];
|
|
qcom,aux-cfg7-settings = [3c 03];
|
|
qcom,aux-cfg8-settings = [40 b7];
|
|
qcom,aux-cfg9-settings = [44 03];
|
|
|
|
qcom,max-pclk-frequency-khz = <675000>;
|
|
|
|
qcom,mst-enable;
|
|
qcom,dp-aux-bridge-sim = <&sde_dp_mst_sim>;
|
|
qcom,dsc-feature-enable;
|
|
qcom,fec-feature-enable;
|
|
qcom,widebus-enable;
|
|
qcom,max-dp-dsc-blks = <2>;
|
|
qcom,max-dp-dsc-input-width-pixs = <2048>;
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1200000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <21800>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <880000>;
|
|
qcom,supply-enable-load = <36000>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0>;
|
|
qcom,supply-max-voltage = <0>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sde_dp1: qcom,dp_display@1{
|
|
cell-index = <1>;
|
|
compatible = "qcom,dp-display";
|
|
qcom,intf-index = <2>;
|
|
qcom,phy-index = <1>;
|
|
|
|
reg = <0xae98000 0x0dc>,
|
|
<0xae98200 0x0c0>,
|
|
<0xae98400 0x508>,
|
|
<0xae98a00 0x094>,
|
|
<0x88efa00 0x200>,
|
|
<0x88ef200 0x200>,
|
|
<0x88ef600 0x200>,
|
|
<0xaf02000 0x1a0>,
|
|
<0x780000 0x621c>,
|
|
<0x88ef040 0x10>,
|
|
<0x88ed000 0x20>,
|
|
<0xaee2000 0x034>,
|
|
<0xae99000 0x094>;
|
|
reg-names = "dp_ahb", "dp_aux", "dp_link",
|
|
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
|
|
"dp_mmss_cc", "qfprom_physical", "dp_pll",
|
|
"usb3_dp_com", "hdcp_physical", "dp_p1";
|
|
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <13 0>;
|
|
|
|
clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
|
|
<&clock_rpmh RPMH_CXO_CLK>,
|
|
<&clock_gcc GCC_USB3_SEC_CLKREF_CLK>,
|
|
<&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_CRYPTO1_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>,
|
|
<&mdss_dp1_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
|
|
<&mdss_dp1_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>,
|
|
<&mdss_dp2_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
|
|
clock-names = "core_aux_clk", "core_usb_ref_clk_src",
|
|
"core_usb_ref_clk", "core_usb_pipe_clk",
|
|
"link_clk", "link_iface_clk",
|
|
"crypto_clk", "pixel_clk_rcg", "pixel_parent",
|
|
"pixel1_clk_rcg", "pixel1_parent",
|
|
"strm0_pixel_clk", "strm1_pixel_clk",
|
|
"bond_pixel_parent";
|
|
|
|
qcom,phy-version = <0x420>;
|
|
qcom,phy-mode = "dp";
|
|
qcom,aux-cfg0-settings = [20 00];
|
|
qcom,aux-cfg1-settings = [24 13];
|
|
qcom,aux-cfg2-settings = [28 24];
|
|
qcom,aux-cfg3-settings = [2c 00];
|
|
qcom,aux-cfg4-settings = [30 0a];
|
|
qcom,aux-cfg5-settings = [34 26];
|
|
qcom,aux-cfg6-settings = [38 0a];
|
|
qcom,aux-cfg7-settings = [3c 03];
|
|
qcom,aux-cfg8-settings = [40 b7];
|
|
qcom,aux-cfg9-settings = [44 03];
|
|
|
|
qcom,max-pclk-frequency-khz = <675000>;
|
|
|
|
qcom,dsc-feature-enable;
|
|
qcom,fec-feature-enable;
|
|
qcom,widebus-enable;
|
|
qcom,max-dp-dsc-blks = <2>;
|
|
qcom,max-dp-dsc-input-width-pixs = <2048>;
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1200000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <21800>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <880000>;
|
|
qcom,supply-enable-load = <36000>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0>;
|
|
qcom,supply-max-voltage = <0>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sde_edp: qcom,dp_display@2{
|
|
cell-index = <2>;
|
|
compatible = "qcom,dp-display";
|
|
qcom,intf-index = <3>;
|
|
qcom,phy-index = <3>;
|
|
|
|
reg = <0xae9a000 0x0dc>,
|
|
<0xae9a200 0x0c0>,
|
|
<0xae9a400 0x508>,
|
|
<0xae9aa00 0x094>,
|
|
<0xaec2a00 0x200>,
|
|
<0xaec2200 0x200>,
|
|
<0xaec2600 0x200>,
|
|
<0xaf02000 0x2ac>,
|
|
<0x780000 0x621c>,
|
|
<0xaec2040 0x10>,
|
|
<0x88e8000 0x20>,
|
|
<0xaee1000 0x034>,
|
|
<0xae9b000 0x094>;
|
|
/* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */
|
|
reg-names = "dp_ahb", "dp_aux", "dp_link",
|
|
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
|
|
"dp_mmss_cc", "qfprom_physical", "dp_pll",
|
|
"usb3_dp_com", "hdcp_physical", "dp_p1";
|
|
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <14 0>;
|
|
|
|
clocks = <&clock_dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
|
|
<&clock_gcc GCC_PCIE_0_CLKREF_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>,
|
|
<&mdss_edp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
|
|
<&clock_dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>,
|
|
<&mdss_dp2_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
|
|
clock-names = "core_aux_clk", "core_ref_clk",
|
|
"link_clk", "link_iface_clk",
|
|
"pixel_clk_rcg", "pixel_parent",
|
|
"strm0_pixel_clk",
|
|
"bond_pixel_parent";
|
|
|
|
qcom,phy-version = <0x500>;
|
|
qcom,phy-mode = "edp";
|
|
qcom,aux-cfg0-settings = [24 00];
|
|
qcom,aux-cfg1-settings = [28 13];
|
|
qcom,aux-cfg2-settings = [2c 24];
|
|
qcom,aux-cfg3-settings = [30 00];
|
|
qcom,aux-cfg4-settings = [34 0a];
|
|
qcom,aux-cfg5-settings = [38 26];
|
|
qcom,aux-cfg6-settings = [3c 0a];
|
|
qcom,aux-cfg7-settings = [40 03];
|
|
qcom,aux-cfg8-settings = [44 37];
|
|
qcom,aux-cfg9-settings = [48 03];
|
|
|
|
qcom,max-pclk-frequency-khz = <675000>;
|
|
|
|
qcom,dsc-feature-enable;
|
|
qcom,fec-feature-enable;
|
|
qcom,widebus-enable;
|
|
qcom,max-dp-dsc-blks = <2>;
|
|
qcom,max-dp-dsc-input-width-pixs = <2048>;
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1200000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <21800>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <880000>;
|
|
qcom,supply-enable-load = <36000>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0>;
|
|
qcom,supply-max-voltage = <0>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|