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379 lines
14 KiB
379 lines
14 KiB
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/qcom,gcc-sdmmagpie.h>
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#include <dt-bindings/msm/msm-bus-ids.h>
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&soc {
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x0a600000 0x100000>;
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reg-names = "core_base";
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iommus = <&apps_smmu 0x540 0x0>;
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qcom,smmu-s1-bypass;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"ss_phy_irq", "dm_hs_phy_irq";
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USB3_GDSC-supply = <&usb30_prim_gdsc>;
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dpdm-supply = <&qusb_phy0>;
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qcom,use-pdc-interrupts;
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clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk", "xo";
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resets = <&clock_gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <133333333>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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qcom,gsi-disable-io-coherency;
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qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
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qcom,pm-qos-latency = <62>;
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qcom,msm-bus,name = "usb0";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <3>;
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qcom,msm-bus,vectors-KBps =
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/* suspend vote */
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<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>,
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<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>,
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/* nominal vote */
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<MSM_BUS_MASTER_USB3
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MSM_BUS_SLAVE_EBI_CH0 1000000 2500000>,
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<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
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/* svs vote */
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<MSM_BUS_MASTER_USB3
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MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
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<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
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/* min vote */
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<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 1 1>,
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<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>;
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0x0a600000 0xcd00>;
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interrupts = <0 133 0>;
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usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3_lpm_capable;
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usb-core-id = <0>;
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tx-fifo-resize;
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maximum-speed = "super-speed";
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dr_mode = "otg";
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};
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qcom,usbbam@a704000 {
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compatible = "qcom,usb-bam-msm";
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reg = <0xa704000 0x17000>;
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interrupts = <0 132 0>;
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qcom,usb-bam-fifo-baseaddr = <0x146a6000>;
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qcom,usb-bam-num-pipes = <4>;
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qcom,disable-clk-gating;
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qcom,usb-bam-override-threshold = <0x4001>;
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qcom,usb-bam-max-mbps-highspeed = <400>;
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qcom,usb-bam-max-mbps-superspeed = <3600>;
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qcom,reset-bam-on-connect;
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qcom,pipe0 {
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label = "ssusb-qdss-in-0";
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qcom,usb-bam-mem-type = <2>;
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qcom,dir = <1>;
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qcom,pipe-num = <0>;
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qcom,peer-bam = <0>;
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qcom,peer-bam-physical-address = <0x6064000>;
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qcom,src-bam-pipe-index = <0>;
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qcom,dst-bam-pipe-index = <0>;
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qcom,data-fifo-offset = <0x0>;
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qcom,data-fifo-size = <0x1800>;
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qcom,descriptor-fifo-offset = <0x1800>;
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qcom,descriptor-fifo-size = <0x800>;
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};
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};
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};
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/* Primary USB port related QUSB2 PHY */
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qusb_phy0: qusb@88e2000 {
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compatible = "qcom,qusb2phy-v2";
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reg = <0x088e2000 0x400>,
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<0x00780200 0x4>,
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<0x088e7014 0x4>;
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reg-names = "qusb_phy_base", "efuse_addr",
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"refgen_north_bg_reg_addr";
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qcom,efuse-bit-pos = <25>;
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qcom,efuse-num-bits = <3>;
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vdd-supply = <&pm6150_l4>;
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vdda18-supply = <&pm6150_l11>;
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vdda33-supply = <&pm6150_l17>;
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qcom,vdd-voltage-level = <0 880000 880000>;
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qcom,qusb-phy-reg-offset =
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<0x240 /* QUSB2PHY_PORT_TUNE1 */
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0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */
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0x210 /* QUSB2PHY_PWR_CTRL1 */
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0x230 /* QUSB2PHY_INTR_CTRL */
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0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */
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0x254 /* QUSB2PHY_TEST1 */
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0x198 /* PLL_BIAS_CONTROL_2 */
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0x27c /* QUSB2PHY_DEBUG_CTRL1 */
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0x280 /* QUSB2PHY_DEBUG_CTRL2 */
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0x284 /* QUSB2PHY_DEBUG_CTRL3 */
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0x288 /* QUSB2PHY_DEBUG_CTRL4 */
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0x2a0>; /* QUSB2PHY_STAT5 */
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qcom,qusb-phy-init-seq =
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/* <value reg_offset> */
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<0x23 0x210 /* PWR_CTRL1 */
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0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
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0x7c 0x18c /* PLL_CLOCK_INVERTERS */
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0x80 0x2c /* PLL_CMODE */
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0x0a 0x184 /* PLL_LOCK_DELAY */
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0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
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0x40 0x194 /* PLL_BIAS_CONTROL_1 */
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0x22 0x198 /* PLL_BIAS_CONTROL_2 */
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0x21 0x214 /* PWR_CTRL2 */
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0x08 0x220 /* IMP_CTRL1 */
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0x58 0x224 /* IMP_CTRL2 */
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0x45 0x240 /* TUNE1 */
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0x29 0x244 /* TUNE2 */
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0xca 0x248 /* TUNE3 */
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0x04 0x24c /* TUNE4 */
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0x03 0x250 /* TUNE5 */
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0x30 0x23c /* CHG_CTRL2 */
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0x22 0x210>; /* PWR_CTRL1 */
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qcom,qusb-phy-host-init-seq =
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/* <value reg_offset> */
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<0x23 0x210 /* PWR_CTRL1 */
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0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
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0x7c 0x18c /* PLL_CLOCK_INVERTERS */
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0x80 0x2c /* PLL_CMODE */
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0x0a 0x184 /* PLL_LOCK_DELAY */
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0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
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0x40 0x194 /* PLL_BIAS_CONTROL_1 */
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0x22 0x198 /* PLL_BIAS_CONTROL_2 */
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0x21 0x214 /* PWR_CTRL2 */
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0x08 0x220 /* IMP_CTRL1 */
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0x58 0x224 /* IMP_CTRL2 */
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0x45 0x240 /* TUNE1 */
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0x29 0x244 /* TUNE2 */
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0xca 0x248 /* TUNE3 */
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0x04 0x24c /* TUNE4 */
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0x03 0x250 /* TUNE5 */
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0x30 0x23c /* CHG_CTRL2 */
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0x22 0x210>; /* PWR_CTRL1 */
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phy_type= "utmi";
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clocks = <&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
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clock-names = "ref_clk_src", "cfg_ahb_clk";
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resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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};
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/* Primary USB port related QMP USB DP Combo PHY */
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usb_qmp_dp_phy: ssphy@88e8000 {
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compatible = "qcom,usb-ssphy-qmp-dp-combo";
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reg = <0x88e8000 0x3000>;
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reg-names = "qmp_phy_base";
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vdd-supply = <&pm6150_l4>;
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qcom,vdd-voltage-level = <0 880000 880000>;
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core-supply = <&pm6150l_l3>;
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qcom,vbus-valid-override;
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qcom,qmp-phy-init-seq =
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/* <reg_offset, value, delay> */
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<0x1048 0x07 0x00 /* COM_PLL_IVCO */
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0x1080 0x14 0x00 /* COM_SYSCLK_EN_SEL */
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0x1034 0x08 0x00 /* COM_BIAS_EN_CLKBUFLR_EN */
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0x1138 0x30 0x00 /* COM_CLK_SELECT */
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0x103c 0x02 0x00 /* COM_SYS_CLK_CTRL */
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0x108c 0x08 0x00 /* COM_RESETSM_CNTRL2 */
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0x115c 0x16 0x00 /* COM_CMN_CONFIG */
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0x1164 0x01 0x00 /* COM_SVS_MODE_CLK_SEL */
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0x113c 0x80 0x00 /* COM_HSCLK_SEL */
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0x10b0 0x82 0x00 /* COM_DEC_START_MODE0 */
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0x10b8 0xab 0x00 /* COM_DIV_FRAC_START1_MODE0 */
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0x10bc 0xea 0x00 /* COM_DIV_FRAC_START2_MODE0 */
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0x10c0 0x02 0x00 /* COM_DIV_FRAC_START3_MODE0 */
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0x1060 0x06 0x00 /* COM_CP_CTRL_MODE0 */
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0x1068 0x16 0x00 /* COM_PLL_RCTRL_MODE0 */
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0x1070 0x36 0x00 /* COM_PLL_CCTRL_MODE0 */
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0x10dc 0x00 0x00 /* COM_INTEGLOOP_GAIN1_MODE0 */
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0x10d8 0x3f 0x00 /* COM_INTEGLOOP_GAIN0_MODE0 */
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0x10f8 0x01 0x00 /* COM_VCO_TUNE2_MODE0 */
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0x10f4 0xc9 0x00 /* COM_VCO_TUNE1_MODE0 */
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0x1148 0x0a 0x00 /* COM_CORECLK_DIV_MODE0 */
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0x10a0 0x00 0x00 /* COM_LOCK_CMP3_MODE0 */
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0x109c 0x34 0x00 /* COM_LOCK_CMP2_MODE0 */
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0x1098 0x15 0x00 /* COM_LOCK_CMP1_MODE0 */
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0x1090 0x04 0x00 /* COM_LOCK_CMP_EN */
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0x1154 0x00 0x00 /* COM_CORE_CLK_EN */
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0x1094 0x00 0x00 /* COM_LOCK_CMP_CFG */
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0x10f0 0x00 0x00 /* COM_VCO_TUNE_MAP */
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0x1040 0x0a 0x00 /* COM_SYSCLK_BUF_ENABLE */
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0x1010 0x01 0x00 /* COM_SSC_EN_CENTER */
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0x101c 0x31 0x00 /* COM_SSC_PER1 */
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0x1020 0x01 0x00 /* COM_SSC_PER2 */
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0x1014 0x00 0x00 /* COM_SSC_ADJ_PER1 */
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0x1018 0x00 0x00 /* COM_SSC_ADJ_PER2 */
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0x1024 0x85 0x00 /* COM_SSC_STEP_SIZE1 */
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0x1028 0x07 0x00 /* COM_SSC_STEP_SIZE2 */
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0x1430 0x0b 0x00 /* RXA_UCDR_FASTLOCK_FO_GAIN */
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0x14d4 0x0f 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL2 */
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0x14d8 0x4e 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL3 */
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0x14dc 0x18 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL4 */
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0x14f8 0x77 0x00 /* RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
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0x14fc 0x80 0x00 /* RXA_RX_OFFSET_ADAPTOR_CNTRL2 */
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0x1504 0x03 0x00 /* RXA_SIGDET_CNTRL */
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0x150c 0x16 0x00 /* RXA_SIGDET_DEGLITCH_CNTRL */
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0x1564 0x05 0x00 /* RXA_RX_MODE_00 */
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0x14c0 0x03 0x00 /* RXA_VGA_CAL_CNTRL2 */
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0x1830 0x0b 0x00 /* RXB_UCDR_FASTLOCK_FO_GAIN */
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0x18d4 0x0f 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL2 */
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0x18d8 0x4e 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL3 */
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0x18dc 0x18 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL4 */
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0x18f8 0x77 0x00 /* RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
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0x18fc 0x80 0x00 /* RXB_RX_OFFSET_ADAPTOR_CNTRL2 */
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0x1904 0x03 0x00 /* RXB_SIGDET_CNTRL */
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0x190c 0x16 0x00 /* RXB_SIGDET_DEGLITCH_CNTRL */
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0x1964 0x05 0x00 /* RXB_RX_MODE_00 */
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0x18c0 0x03 0x00 /* RXB_VGA_CAL_CNTRL2 */
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0x1260 0x10 0x00 /* TXA_HIGHZ_DRVR_EN */
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0x12a4 0x12 0x00 /* TXA_RCV_DETECT_LVL_2 */
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0x128c 0x16 0x00 /* TXA_LANE_MODE_1 */
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0x1248 0x09 0x00 /* TXA_RES_CODE_LANE_OFFSET_RX */
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0x1244 0x06 0x00 /* TXA_RES_CODE_LANE_OFFSET_TX */
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0x1660 0x10 0x00 /* TXB_HIGHZ_DRVR_EN */
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0x16a4 0x12 0x00 /* TXB_RCV_DETECT_LVL_2 */
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0x168c 0x16 0x00 /* TXB_LANE_MODE_1 */
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0x1648 0x09 0x00 /* TXB_RES_CODE_LANE_OFFSET_RX */
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0x1644 0x06 0x00 /* TXB_RES_CODE_LANE_OFFSET_TX */
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0x1cc8 0x83 0x00 /* PCS_FLL_CNTRL2 */
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0x1ccc 0x09 0x00 /* PCS_FLL_CNT_VAL_L */
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0x1cd0 0xa2 0x00 /* PCS_FLL_CNT_VAL_H_TOL */
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0x1cd4 0x40 0x00 /* PCS_FLL_MAN_CODE */
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0x1cc4 0x02 0x00 /* PCS_FLL_CNTRL1 */
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0x1c80 0xd1 0x00 /* PCS_LOCK_DETECT_CONFIG1 */
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0x1c84 0x1f 0x00 /* PCS_LOCK_DETECT_CONFIG2 */
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0x1c88 0x47 0x00 /* PCS_LOCK_DETECT_CONFIG3 */
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0x1c64 0x1b 0x00 /* PCS_POWER_STATE_CONFIG2 */
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0x1434 0x75 0x00 /* RXA_UCDR_SO_SATURATION */
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0x1834 0x75 0x00 /* RXB_UCDR_SO_SATURATION */
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0x1dd8 0xba 0x00 /* PCS_RX_SIGDET_LVL */
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0x1c0c 0x9f 0x00 /* PCS_TXMGN_V0 */
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0x1c10 0x9f 0x00 /* PCS_TXMGN_V1 */
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0x1c14 0xb7 0x00 /* PCS_TXMGN_V2 */
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0x1c18 0x4e 0x00 /* PCS_TXMGN_V3 */
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0x1c1c 0x65 0x00 /* PCS_TXMGN_V4 */
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0x1c20 0x6b 0x00 /* PCS_TXMGN_LS */
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0x1c24 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V0 */
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0x1c28 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V0 */
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0x1c2c 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V1 */
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0x1c30 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V1 */
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0x1c34 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V2 */
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0x1c38 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V2 */
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0x1c3c 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V3 */
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0x1c40 0x1d 0x00 /* PCS_TXDEEMPH_M3P5DB_V3 */
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0x1c44 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V4 */
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0x1c48 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V4 */
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0x1c4c 0x15 0x00 /* PCS_TXDEEMPH_M6DB_LS */
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0x1c50 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_LS */
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0x1e0c 0x21 0x00 /* PCS_REFGEN_REQ_CONFIG1 */
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0x1e10 0x60 0x00 /* PCS_REFGEN_REQ_CONFIG2 */
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0x1c5c 0x02 0x00 /* PCS_RATE_SLEW_CNTRL */
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0x1ca0 0x04 0x00 /* PCS_PWRUP_RESET_DLY_TIME_AUXCLK */
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0x1c8c 0x44 0x00 /* PCS_TSYNC_RSYNC_TIME */
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0x1c70 0xe7 0x00 /* PCS_RCVR_DTCT_DLY_P1U2_L */
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0x1c74 0x03 0x00 /* PCS_RCVR_DTCT_DLY_P1U2_H */
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0x1c78 0x40 0x00 /* PCS_RCVR_DTCT_DLY_U3_L */
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0x1c7c 0x00 0x00 /* PCS_RCVR_DTCT_DLY_U3_H */
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0x1cb8 0x75 0x00 /* PCS_RXEQTRAINING_WAIT_TIME */
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0x1cb0 0x86 0x00 /* PCS_LFPS_TX_ECSTART_EQTLOCK */
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0x1cbc 0x13 0x00 /* PCS_RXEQTRAINING_RUN_TIME */
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0x1cac 0x04 0x00 /* PCS_LFPS_DET_HIGH_COUNT_VAL */
|
|
0xffffffff 0xffffffff 0x00>;
|
|
|
|
qcom,qmp-phy-reg-offset =
|
|
<0x1d74 /* USB3_DP_PCS_PCS_STATUS */
|
|
0x1cd8 /* USB3_DP_PCS_AUTONOMOUS_MODE_CTRL */
|
|
0x1cdc /* USB3_DP_PCS_LFPS_RXTERM_IRQ_CLEAR */
|
|
0x1c04 /* USB3_DP_PCS_POWER_DOWN_CONTROL */
|
|
0x1c00 /* USB3_DP_PCS_SW_RESET */
|
|
0x1c08 /* USB3_DP_PCS_START_CONTROL */
|
|
0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
|
|
0x2a18 /* USB3_DP_DP_PHY_PD_CTL */
|
|
0x0008 /* USB3_DP_COM_POWER_DOWN_CTRL */
|
|
0x0004 /* USB3_DP_COM_SW_RESET */
|
|
0x001c /* USB3_DP_COM_RESET_OVRD_CTRL */
|
|
0x0000 /* USB3_DP_COM_PHY_MODE_CTRL */
|
|
0x0010 /* USB3_DP_COM_TYPEC_CTRL */
|
|
0x000c /* USB3_DP_COM_SWI_CTRL */
|
|
0x1a0c>; /* USB3_DP_PCS_MISC_CLAMP_ENABLE */
|
|
|
|
clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
|
|
<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
|
<&clock_rpmh RPMH_CXO_CLK>,
|
|
<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
|
|
<&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
|
|
<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
|
|
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
|
|
"ref_clk", "com_aux_clk", "cfg_ahb_clk";
|
|
|
|
resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>,
|
|
<&clock_gcc GCC_USB3_PHY_PRIM_BCR>;
|
|
reset-names = "global_phy_reset", "phy_reset";
|
|
};
|
|
|
|
usb_audio_qmi_dev {
|
|
compatible = "qcom,usb-audio-qmi-dev";
|
|
iommus = <&apps_smmu 0x1b2f 0x0>;
|
|
qcom,usb-audio-stream-id = <0xf>;
|
|
qcom,usb-audio-intr-num = <2>;
|
|
};
|
|
|
|
usb_nop_phy: usb_nop_phy {
|
|
compatible = "usb-nop-xceiv";
|
|
};
|
|
};
|
|
|