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114 lines
3.1 KiB
114 lines
3.1 KiB
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94a00 {
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compatible = "qcom,mdss_dsi_pll_10nm";
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label = "MDSS DSI 0 PLL";
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cell-index = <0>;
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#clock-cells = <1>;
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reg = <0xae94a00 0x1e0>,
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<0xae94400 0x800>,
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<0xaf03000 0x8>,
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<0xae94200 0x100>;
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reg-names = "pll_base", "phy_base", "gdsc_base",
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"dynamic_pll_base";
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clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
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clock-names = "iface_clk";
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clock-rate = <0>;
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memory-region = <&dfps_data_memory>;
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gdsc-supply = <&mdss_core_gdsc>;
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "gdsc";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96a00 {
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compatible = "qcom,mdss_dsi_pll_10nm";
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label = "MDSS DSI 1 PLL";
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cell-index = <1>;
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#clock-cells = <1>;
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reg = <0xae96a00 0x1e0>,
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<0xae96400 0x800>,
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<0xaf03000 0x8>,
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<0xae96200 0x100>;
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reg-names = "pll_base", "phy_base", "gdsc_base",
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"dynamic_pll_base";
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clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
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clock-names = "iface_clk";
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clock-rate = <0>;
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gdsc-supply = <&mdss_core_gdsc>;
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "gdsc";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_dp_pll: qcom,mdss_dp_pll@ae90000 {
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compatible = "qcom,mdss_dp_pll_10nm";
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label = "MDSS DP PLL";
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cell-index = <0>;
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#clock-cells = <1>;
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reg = <0x088ea000 0x200>,
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<0x088eaa00 0x200>,
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<0x088ea200 0x200>,
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<0x088ea600 0x200>,
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<0xaf03000 0x8>;
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reg-names = "pll_base", "phy_base", "ln_tx0_base",
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"ln_tx1_base", "gdsc_base";
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gdsc-supply = <&mdss_core_gdsc>;
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clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
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<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "iface_clk", "ref_clk_src", "ref_clk",
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"cfg_ahb_clk", "pipe_clk";
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clock-rate = <0>;
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "gdsc";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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};
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