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703 lines
15 KiB
703 lines
15 KiB
/* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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pil_gpu: qcom,kgsl-hyp {
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compatible = "qcom,pil-tz-generic";
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qcom,pas-id = <13>;
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qcom,firmware-name = "a512_zap";
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};
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msm_bus: qcom,kgsl-busmon{
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label = "kgsl-busmon";
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compatible = "qcom,kgsl-busmon";
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};
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gpu_bw_tbl: gpu-bw-tbl {
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compatible = "operating-points-v2";
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opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */
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opp-100 { opp-hz = /bits/ 64 < 381 >; }; /* 1.100 MHz */
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opp-150 { opp-hz = /bits/ 64 < 572 >; }; /* 2.150 MHz */
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opp-200 { opp-hz = /bits/ 64 < 762 >; }; /* 3.200 MHz */
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opp-300 { opp-hz = /bits/ 64 < 1144 >; }; /* 4.300 MHz */
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opp-412 { opp-hz = /bits/ 64 < 1571 >; }; /* 5.412 MHz */
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opp-547 { opp-hz = /bits/ 64 < 2086 >; }; /* 6.547 MHz */
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opp-681 { opp-hz = /bits/ 64 < 2597 >; }; /* 7.681 MHz */
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opp-768 { opp-hz = /bits/ 64 < 2929 >; }; /* 8.768 MHz */
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opp-1017 { opp-hz = /bits/ 64 < 3879 >; }; /* 9.1017 MHz */
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opp-1296 { opp-hz = /bits/ 64 < 4943 >; }; /* 10.1296 MHz */
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opp-1353 { opp-hz = /bits/ 64 < 5161 >; }; /* 11.1353 MHz */
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opp-1555 { opp-hz = /bits/ 64 < 5931 >; }; /* 12.1555 MHz */
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opp-1804 { opp-hz = /bits/ 64 < 6881 >; }; /* 13.1804 MHz */
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};
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gpubw: qcom,gpubw {
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compatible = "qcom,devbw";
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governor = "bw_vbif";
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qcom,src-dst-ports = <26 512>;
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operating-points-v2 = <&gpu_bw_tbl>;
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/*
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* active-only flag is used while registering the bus
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* governor. It helps release the bus vote when the CPU
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* subsystem is inactive
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*/
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qcom,active-only;
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};
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msm_gpu: qcom,kgsl-3d0@5000000 {
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label = "kgsl-3d0";
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compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
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status = "ok";
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reg = <0x5000000 0x40000
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0x780000 0x6220>;
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reg-names = "kgsl_3d0_reg_memory", "qfprom_memory";
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interrupts = <0 300 0>;
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interrupt-names = "kgsl_3d0_irq";
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qcom,id = <0>;
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qcom,chipid = <0x05010200>;
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qcom,initial-pwrlevel = <6>;
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/* <HZ/12> */
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qcom,idle-timeout = <80>;
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qcom,highest-bank-bit = <14>;
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/* size in bytes */
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qcom,snapshot-size = <1048576>;
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#cooling-cells = <2>;
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clocks = <&clock_gfx GPUCC_GFX3D_CLK>,
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<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
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<&clock_gfx GPUCC_RBBMTIMER_CLK>,
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<&clock_gcc GCC_GPU_BIMC_GFX_CLK>,
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<&clock_gcc GCC_BIMC_GFX_CLK>,
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<&clock_gpu GPUCC_RBCPR_CLK>;
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clock-names = "core_clk", "iface_clk", "rbbmtimer_clk",
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"mem_clk", "alt_mem_iface_clk", "rbcpr_clk";
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/* Bus Scale Settings */
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qcom,gpubw-dev = <&gpubw>;
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qcom,bus-control;
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/* GPU to BIMC bus width, VBIF data transfer in 1 cycle */
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qcom,bus-width = <32>;
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qcom,msm-bus,name = "grp3d";
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qcom,msm-bus,num-cases = <14>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<26 512 0 0>,
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<26 512 0 400000>, /* 1 bus=100 */
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<26 512 0 600000>, /* 2 bus=150 */
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<26 512 0 800000>, /* 3 bus=200 */
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<26 512 0 1200000>, /* 4 bus=300 */
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<26 512 0 1648000>, /* 5 bus=412 */
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<26 512 0 2188000>, /* 6 bus=547 */
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<26 512 0 2724000>, /* 7 bus=681 */
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<26 512 0 3072000>, /* 8 bus=768 */
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<26 512 0 4068000>, /* 9 bus=1017 */
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<26 512 0 5184000>, /* 10 bus=1296 */
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<26 512 0 5412000>, /* 11 bus=1353 */
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<26 512 0 6220000>, /* 12 bus=1555 */
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<26 512 0 7216000>; /* 13 bus=1804 */
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/* GDSC regulator names */
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regulator-names = "vddcx", "vdd";
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/* GDSC oxili regulators */
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vddcx-supply = <&gdsc_gpu_cx>;
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vdd-supply = <&gdsc_gpu_gx>;
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/* Cx ipeak limit supprt */
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qcom,gpu-cx-ipeak = <&cx_ipeak_lm 1>;
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qcom,gpu-cx-ipeak-clk = <700000000>;
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/* CPU latency parameter */
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qcom,pm-qos-active-latency = <518>;
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qcom,pm-qos-wakeup-latency = <518>;
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/* Quirks */
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qcom,gpu-quirk-dp2clockgating-disable;
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qcom,gpu-quirk-lmloadkill-disable;
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/* Enable context aware freq. scaling */
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qcom,enable-ca-jump;
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/* Context aware jump busy penalty in us */
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qcom,ca-busy-penalty = <12000>;
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/* Context aware jump target power level */
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qcom,ca-target-pwrlevel = <4>;
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qcom,gpu-speed-bin = <0x41a0 0x1fe00000 21>;
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/* GPU Mempools */
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qcom,gpu-mempools {
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#address-cells= <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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qcom,mempool-max-pages = <32768>;
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-allocate;
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};
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};
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/*
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* Speed-bin zero is default speed bin.
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* For rest of the speed bins, speed-bin value
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* is calulated as FMAX/4.8 MHz round up to zero
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* decimal places.
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*/
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible="qcom,gpu-pwrlevel-bins";
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <0>;
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qcom,initial-pwrlevel = <6>;
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/* TURBO */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <750000000>;
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qcom,bus-freq = <13>;
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qcom,bus-min = <12>;
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qcom,bus-max = <13>;
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};
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <700000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <11>;
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qcom,bus-max = <13>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <647000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <12>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <588000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <12>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <465000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <11>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <370000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <6>;
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qcom,bus-max = <9>;
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};
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/* Low SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <266000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <3>;
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qcom,bus-max = <6>;
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};
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/* Min SVS */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <160000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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/* XO */
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <19200000>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <157>;
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qcom,initial-pwrlevel = <6>;
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/* TURBO */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <750000000>;
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qcom,bus-freq = <13>;
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qcom,bus-min = <12>;
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qcom,bus-max = <13>;
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};
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <700000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <11>;
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qcom,bus-max = <13>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <647000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <12>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <588000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <12>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <465000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <11>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <370000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <6>;
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qcom,bus-max = <9>;
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};
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/* Low SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <266000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <3>;
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qcom,bus-max = <6>;
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};
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/* Min SVS */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <160000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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/* XO */
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <19200000>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-2 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <146>;
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qcom,initial-pwrlevel = <5>;
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/* TURBO */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <700000000>;
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qcom,bus-freq = <13>;
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qcom,bus-min = <12>;
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qcom,bus-max = <13>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <647000000>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <10>;
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qcom,bus-max = <12>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <588000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <12>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <465000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <11>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <370000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <6>;
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qcom,bus-max = <9>;
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};
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/* Low SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <266000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <3>;
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qcom,bus-max = <6>;
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};
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/* Min SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <160000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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/* XO */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <19200000>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-3 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <135>;
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qcom,initial-pwrlevel = <4>;
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/* NOM_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <647000000>;
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qcom,bus-freq = <13>;
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qcom,bus-min = <12>;
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qcom,bus-max = <13>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <588000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <12>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <465000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <11>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <370000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <6>;
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qcom,bus-max = <9>;
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};
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/* Low SVS */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <266000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <3>;
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qcom,bus-max = <6>;
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};
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/* Min SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <160000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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/* XO */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <19200000>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-4 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <78>;
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qcom,initial-pwrlevel = <1>;
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|
|
/* SVS */
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0>;
|
|
qcom,gpu-freq = <370000000>;
|
|
qcom,bus-freq = <8>;
|
|
qcom,bus-min = <6>;
|
|
qcom,bus-max = <11>;
|
|
};
|
|
|
|
/* Low SVS */
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <1>;
|
|
qcom,gpu-freq = <266000000>;
|
|
qcom,bus-freq = <3>;
|
|
qcom,bus-min = <3>;
|
|
qcom,bus-max = <6>;
|
|
};
|
|
|
|
/* Min SVS */
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <2>;
|
|
qcom,gpu-freq = <160000000>;
|
|
qcom,bus-freq = <3>;
|
|
qcom,bus-min = <3>;
|
|
qcom,bus-max = <5>;
|
|
};
|
|
|
|
/* XO */
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <3>;
|
|
qcom,gpu-freq = <19200000>;
|
|
qcom,bus-freq = <0>;
|
|
qcom,bus-min = <0>;
|
|
qcom,bus-max = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevels-5 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,speed-bin = <90>;
|
|
|
|
qcom,initial-pwrlevel = <2>;
|
|
|
|
/* SVS_L1 */
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0>;
|
|
qcom,gpu-freq = <430000000>;
|
|
qcom,bus-freq = <11>;
|
|
qcom,bus-min = <10>;
|
|
qcom,bus-max = <11>;
|
|
};
|
|
|
|
/* SVS */
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <1>;
|
|
qcom,gpu-freq = <370000000>;
|
|
qcom,bus-freq = <8>;
|
|
qcom,bus-min = <6>;
|
|
qcom,bus-max = <11>;
|
|
};
|
|
|
|
/* Low SVS */
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <2>;
|
|
qcom,gpu-freq = <266000000>;
|
|
qcom,bus-freq = <3>;
|
|
qcom,bus-min = <3>;
|
|
qcom,bus-max = <6>;
|
|
};
|
|
|
|
/* Min SVS */
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <3>;
|
|
qcom,gpu-freq = <160000000>;
|
|
qcom,bus-freq = <3>;
|
|
qcom,bus-min = <3>;
|
|
qcom,bus-max = <5>;
|
|
};
|
|
|
|
/* XO */
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <4>;
|
|
qcom,gpu-freq = <19200000>;
|
|
qcom,bus-freq = <0>;
|
|
qcom,bus-min = <0>;
|
|
qcom,bus-max = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevels-6 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,speed-bin = <122>;
|
|
|
|
qcom,initial-pwrlevel = <3>;
|
|
|
|
/* NOM */
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0>;
|
|
qcom,gpu-freq = <585000000>;
|
|
qcom,bus-freq = <12>;
|
|
qcom,bus-min = <11>;
|
|
qcom,bus-max = <12>;
|
|
};
|
|
|
|
/* SVS_L1 */
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <1>;
|
|
qcom,gpu-freq = <465000000>;
|
|
qcom,bus-freq = <9>;
|
|
qcom,bus-min = <8>;
|
|
qcom,bus-max = <11>;
|
|
};
|
|
|
|
/* SVS */
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <2>;
|
|
qcom,gpu-freq = <370000000>;
|
|
qcom,bus-freq = <8>;
|
|
qcom,bus-min = <6>;
|
|
qcom,bus-max = <9>;
|
|
};
|
|
|
|
/* Low SVS */
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <3>;
|
|
qcom,gpu-freq = <266000000>;
|
|
qcom,bus-freq = <3>;
|
|
qcom,bus-min = <3>;
|
|
qcom,bus-max = <6>;
|
|
};
|
|
|
|
/* Min SVS */
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <4>;
|
|
qcom,gpu-freq = <160000000>;
|
|
qcom,bus-freq = <3>;
|
|
qcom,bus-min = <3>;
|
|
qcom,bus-max = <5>;
|
|
};
|
|
|
|
/* XO */
|
|
qcom,gpu-pwrlevel@5 {
|
|
reg = <5>;
|
|
qcom,gpu-freq = <19200000>;
|
|
qcom,bus-freq = <0>;
|
|
qcom,bus-min = <0>;
|
|
qcom,bus-max = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
kgsl_msm_iommu: qcom,kgsl-iommu {
|
|
compatible = "qcom,kgsl-smmu-v2";
|
|
|
|
reg = <0x05040000 0x10000>;
|
|
qcom,protect = <0x40000 0x10000>;
|
|
qcom,micro-mmu-control = <0x6000>;
|
|
|
|
clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
|
|
<&clock_gcc GCC_GPU_BIMC_GFX_CLK>,
|
|
<&clock_gcc GCC_BIMC_GFX_CLK>;
|
|
|
|
clock-names = "iface_clk", "mem_clk", "alt_mem_iface_clk";
|
|
|
|
qcom,secure_align_mask = <0xfff>;
|
|
qcom,retention;
|
|
qcom,hyp_secure_alloc;
|
|
|
|
gfx3d_user: gfx3d_user {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
label = "gfx3d_user";
|
|
iommus = <&kgsl_smmu 0>;
|
|
qcom,gpu-offset = <0x48000>;
|
|
};
|
|
|
|
gfx3d_secure: gfx3d_secure {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
iommus = <&kgsl_smmu 2>;
|
|
};
|
|
};
|
|
};
|
|
|