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198 lines
4.2 KiB
198 lines
4.2 KiB
/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/ {
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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};
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CPU0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
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next-level-cache = <&L2_1>;
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#cooling-cells = <2>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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/* A53 L2 dump not supported */
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qcom,dump-size = <0x0>;
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};
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L1_I_100: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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};
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L1_D_100: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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};
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};
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CPU1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
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next-level-cache = <&L2_1>;
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#cooling-cells = <2>;
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L1_I_101: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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};
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L1_D_101: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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};
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};
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CPU2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
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next-level-cache = <&L2_1>;
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#cooling-cells = <2>;
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L1_I_102: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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};
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L1_D_102: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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};
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};
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CPU3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
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next-level-cache = <&L2_1>;
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#cooling-cells = <2>;
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L1_I_103: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x8800>;
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};
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L1_D_103: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x9000>;
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};
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};
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};
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energy_costs: energy-costs {
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compatible = "sched-energy";
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CPU_COST_0: core-cost0 {
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busy-cost-data = <
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960000 159
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1305600 207
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1497600 256
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1708800 327
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>;
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idle-cost-data = <
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100 80 60 40
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>;
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};
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CLUSTER_COST_0: cluster-cost0 {
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busy-cost-data = <
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960000 53
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1305600 61
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1497600 71
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1708800 85
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>;
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idle-cost-data = <
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4 3 2 1
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>;
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};
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};
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};
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&soc {
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cpuss_dump {
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compatible = "qcom,cpuss-dump";
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qcom,l2_dump1 {
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/* L2 cache dump for A53 cluster */
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qcom,dump-node = <&L2_1>;
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qcom,dump-id = <0xC1>;
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};
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qcom,l1_i_cache100 {
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qcom,dump-node = <&L1_I_100>;
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qcom,dump-id = <0x64>;
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};
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qcom,l1_i_cache101 {
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qcom,dump-node = <&L1_I_101>;
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qcom,dump-id = <0x65>;
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};
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qcom,l1_i_cache102 {
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qcom,dump-node = <&L1_I_102>;
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qcom,dump-id = <0x66>;
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};
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qcom,l1_i_cache103 {
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qcom,dump-node = <&L1_I_103>;
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qcom,dump-id = <0x67>;
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};
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qcom,l1_d_cache100 {
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qcom,dump-node = <&L1_D_100>;
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qcom,dump-id = <0x84>;
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};
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qcom,l1_d_cache101 {
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qcom,dump-node = <&L1_D_101>;
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qcom,dump-id = <0x85>;
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};
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qcom,l1_d_cache102 {
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qcom,dump-node = <&L1_D_102>;
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qcom,dump-id = <0x86>;
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};
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qcom,l1_d_cache103 {
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qcom,dump-node = <&L1_D_103>;
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qcom,dump-id = <0x87>;
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};
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};
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};
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