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kernel_samsung_sm7125/arch/arm64/boot/dts/qcom/sa8155-capture.dtsi

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/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "skeleton64.dtsi"
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,tcs-mbox.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/msm/msm-bus-ids.h>
/ {
model = "Qualcomm Technologies, Inc. SM8150";
compatible = "qcom,sa8155";
qcom,msm-name = "SM8150";
interrupt-parent = <&intc>;
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
#cooling-cells = <0x2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <0x2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-level = <0x3>;
};
};
L1_I_0: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
};
L1_D_0: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9000>;
};
L2_TLB_0: l2-tlb {
qcom,dump-size = <0x5000>;
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_1>;
#cooling-cells = <0x2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <0x2>;
next-level-cache = <&L3_0>;
};
L1_I_100: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
};
L1_D_100: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9000>;
};
L2_TLB_100: l2-tlb {
qcom,dump-size = <0x5000>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_2>;
#cooling-cells = <0x2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <0x2>;
next-level-cache = <&L3_0>;
};
L1_I_200: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
};
L1_D_200: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9000>;
};
L2_TLB_200: l2-tlb {
qcom,dump-size = <0x5000>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_3>;
#cooling-cells = <0x2>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <0x2>;
next-level-cache = <&L3_0>;
};
L1_I_300: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
};
L1_D_300: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9000>;
};
L2_TLB_300: l2-tlb {
qcom,dump-size = <0x5000>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_4>;
#cooling-cells = <0x2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <0x2>;
next-level-cache = <&L3_0>;
};
L1_I_400: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
};
L1_D_400: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9000>;
};
L2_TLB_400: l2-tlb {
qcom,dump-size = <0x5000>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_5>;
#cooling-cells = <0x2>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-level = <0x2>;
next-level-cache = <&L3_0>;
};
L1_I_500: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
};
L1_D_500: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9000>;
};
L2_TLB_500: l2-tlb {
qcom,dump-size = <0x5000>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_6>;
#cooling-cells = <0x2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-level = <0x2>;
next-level-cache = <&L3_0>;
};
L1_I_600: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
};
L1_D_600: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9000>;
};
L2_TLB_600: l2-tlb {
qcom,dump-size = <0x5000>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_7>;
#cooling-cells = <0x2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-level = <0x2>;
next-level-cache = <&L3_0>;
};
L1_I_700: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
};
L1_D_700: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x9000>;
};
L2_TLB_700: l2-tlb {
qcom,dump-size = <0x5000>;
};
};
};
soc: soc { } ;
chosen {
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
};
aliases {
serial0 = "/soc/qcom,qup_uart@0xa90000";
};
memory {
device_type = "memory";
reg = <0x1 0x40000000 0x0 0x20000000>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
#include "sm8150-gdsc.dtsi"
&soc {
status = "ok";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0x0 0x0 0x0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17a00000 0x10000>, /* GICD */
<0x17a60000 0x100000>; /* GICR * 8 */
interrupts = <1 9 4>;
interrupt-parent = <&intc>;
};
clock_gcc: qcom,gcc {
compatible = "qcom,gcc-sa8155-v2", "syscon";
reg = <0x100000 0x1f0000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
#clock-cells = <0x1>;
#reset-cells = <0x1>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 1 0xf08>,
<1 2 0xf08>,
<1 3 0xf08>,
<1 0 0xf08>;
clock-frequency = <19200000>;
};
timer@0x17c20000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17c20000 0x1000>;
clock-frequency = <0x124f800>;
frame@0x17c21000 {
frame-number = <0x0>;
interrupts = <0x0 0x8 0x4 0x0 0x6 0x4>;
reg = <0x17c21000 0x1000 0x17c22000 0x1000>;
};
};
wdog: qcom,wdt@17c10000 {
compatible = "qcom,msm-watchdog";
reg = <0x17c10000 0x1000>;
reg-names = "wdt-base";
interrupts = <0 0 0>, <0 1 0>;
qcom,bark-time = <11000>;
qcom,pet-time = <9360>;
qcom,ipi-ping;
qcom,wakeup-enable;
qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100
0x18100 0x18100 0x18100 0x18100>;
};
qcom,msm-imem@146bf000 {
compatible = "qcom,msm-imem";
reg = <0x146bf000 0x1000>;
ranges = <0x0 0x146bf000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
};
restart@c264000 {
compatible = "qcom,pshold";
reg = <0xc264000 0x4>,
<0x1fd3000 0x4>;
reg-names = "pshold-base", "tcsr-boot-misc-detect";
};
apps_rsc: mailbox@18220000 {
compatible = "qcom,tcs-drv";
status="ok";
label = "apps_rsc";
reg = <0x18220000 0x100>, <0x18220d00 0x3000>;
interrupts = <0 5 0>;
#mbox-cells = <1>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
};
clock_rpmh: qcom,rpmhclk {
compatible = "qcom,rpmh-clk-sm8150";
mboxes = <&apps_rsc 0>;
mbox-names = "apps";
#clock-cells = <1>;
};
disp_rsc: mailbox@af20000 {
compatible = "qcom,tcs-drv";
label = "display_rsc";
reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>;
interrupts = <0 129 0>;
#mbox-cells = <1>;
qcom,drv-id = <0>;
qcom,tcs-config = <SLEEP_TCS 1>,
<WAKE_TCS 1>,
<ACTIVE_TCS 2>,
<CONTROL_TCS 0>;
status = "disabled";
};
qmp_aop: qcom,qmp-aop@c300000 {
compatible = "qcom,qmp-mbox";
reg = <0xc300000 0x1000>, <0x17c0000C 0x4>;
reg-names = "msgram", "irq-reg-base";
qcom,irq-mask = <0x1>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
label = "aop";
qcom,early-boot;
priority = <0>;
mbox-desc-offset = <0x0>;
#mbox-cells = <1>;
};
cmd_db: qcom,cmd-db@c3f000c {
compatible = "qcom,cmd-db";
reg = <0xc3f000c 8>;
};
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0xac0000 0x6000>;
qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;
qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
qcom,iommu-s1-bypass;
iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {
compatible = "qcom,qupv3-geni-se-cb";
iommus = <&apps_smmu 0x603 0x0>;
};
};
/* 2-wire UART */
/* Debug UART Instance for CDP/MTP platform */
qupv3_se12_2uart: qcom,qup_uart@0xa90000 {
compatible = "qcom,msm-geni-console";
reg = <0xa90000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se12_2uart_active>;
pinctrl-1 = <&qupv3_se12_2uart_sleep>;
interrupts = <GIC_SPI 357 0>;
qcom,wrapper-core = <&qupv3_1>;
status = "ok";
};
apps_smmu: apps-smmu@0x15000000 {
compatible = "qcom,qsmmu-v500";
reg = <0x15000000 0x100000>,
<0x15182000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,skip-init;
qcom,use-3-lvl-tables;
qcom,disable-atos;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
qcom,msm-bus,name = "apps_smmu";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,active-only;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<MSM_BUS_MASTER_GEM_NOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 0>,
<MSM_BUS_MASTER_GEM_NOC_SNOC>,
<MSM_BUS_SLAVE_IMEM_CFG>,
<0 1000>;
};
ufs_ice: ufsice@1d90000 {
compatible = "qcom,ice";
reg = <0x1d90000 0x8000>;
qcom,enable-ice-clk;
clock-names = "ufs_core_clk", "bus_clk",
"iface_clk", "ice_core_clk";
clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,
<&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;
qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
vdd-hba-supply = <&ufs_phy_gdsc>;
qcom,msm-bus,name = "ufs_ice_noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<1 650 0 0>, /* No vote */
<1 650 1000 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"MAX";
qcom,instance-type = "ufs";
};
ufsphy_mem: ufsphy_mem@1d87000 {
compatible = "qcom,ufs-phy-qmp-v4";
reg = <0x1d87000 0xda8>; /* PHY regs */
reg-names = "phy_mem";
#phy-cells = <0>;
ufs-qcom-crypto = <&ufs_ice>;
lanes-per-direction = <2>;
clock-names = "ref_clk_src",
"ref_clk",
"ref_aux_clk";
clocks = <&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;
vdda-pll-supply = <&pm8150_2_l8>;
vdda-phy-max-microamp = <87100>;
vdda-pll-max-microamp = <18300>;
vdda-phy-supply = <&pm8150_1_l5>;
status = "ok";
};
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x2500>;
interrupts = <0 265 0>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
ufs-qcom-crypto = <&ufs_ice>;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&clock_gcc GCC_UFS_PHY_AXI_CLK>,
<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<37500000 300000000>,
<0 0>,
<0 0>,
<37500000 300000000>,
<37500000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
qcom,msm-bus,name = "ufshc_mem";
qcom,msm-bus,num-cases = <26>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
/*
* During HS G3 UFS runs at nominal voltage corner, vote
* higher bandwidth to push other buses in the data path
* to run at nominal to achieve max throughput.
* 4GBps pushes BIMC to run at nominal.
* 200MBps pushes CNOC to run at nominal.
* Vote for half of this bandwidth for HS G3 1-lane.
* For max bandwidth, vote high enough to push the buses
* to run in turbo voltage corner.
*/
<123 512 0 0>, <1 757 0 0>, /* No vote */
<123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
<123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
<123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
<123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
<123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */
<123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */
<123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */
<123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */
<123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
<123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
<123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
<123 512 4194304 0>, <1 757 204800 0>, /* HS G4 RA */
<123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */
<123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */
<123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */
<123 512 8388608 0>, <1 757 409600 0>, /* HS G4 RA L2 */
<123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
<123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
<123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
<123 512 4194304 0>, <1 757 204800 0>, /* HS G4 RB */
<123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */
<123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */
/* As UFS working in HS G3 RB L2 mode, aggregated
* bandwidth (AB) should take care of providing
* optimum throughput requested. However, as tested,
* in order to scale up CNOC clock, instantaneous
* bindwidth (IB) needs to be given a proper value too.
*/
<123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */
<123 512 8388608 0>, <1 757 409600 409600>, /* HS G4 RB L2 */
<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
"MAX";
/* PM QoS */
qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
qcom,pm-qos-cpu-group-latency-us = <44 44>;
qcom,pm-qos-default-cpu = <0>;
pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
pinctrl-0 = <&ufs_dev_reset_assert>;
pinctrl-1 = <&ufs_dev_reset_deassert>;
resets = <&clock_gcc GCC_UFS_PHY_BCR>;
reset-names = "core_reset";
vdd-hba-supply = <&ufs_phy_gdsc>;
vdd-hba-fixed-regulator;
vcc-supply = <&pm8150_1_l10>;
vcc-voltage-level = <2950000 2960000>;
vccq2-supply = <&pm8150_1_s4>;
vcc-max-microamp = <750000>;
vccq2-max-microamp = <750000>;
qcom,vddp-ref-clk-supply = <&pm8150_2_l5>;
qcom,vddp-ref-clk-max-microamp = <100>;
status = "ok";
};
};
&apps_smmu {
qcom,actlr =
/* HF0 and HF1 TBUs: +3 deep PF */
<0x800 0x7ff 0x103>,
/* SF TBU: +3 deep PF */
<0x2000 0x3ff 0x103>,
/* NPU SIDs: +15 deep PF */
<0x1480 0x3 0x303>,
<0x1484 0x1 0x303>,
<0x1080 0x3 0x303>,
<0x1084 0x1 0x303>;
};
&ufs_phy_gdsc {
status = "ok";
};
#include "sa8155-regulator.dtsi"
#include "sm8150-pinctrl.dtsi"
#include "sm8150-bus.dtsi"