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309 lines
8.3 KiB
309 lines
8.3 KiB
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/qcom,gcc-sm6150.h>
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#include "sa6155-cnss.dtsi"
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#include "sa6155-display.dtsi"
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&qupv3_2 {
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status = "ok";
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};
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&bluetooth_ext {
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status = "ok";
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};
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&qupv3_se6_spi {
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status = "ok";
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can-controller@0 {
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compatible = "qcom,nxp,mpc5746c";
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reg = <0>;
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interrupt-parent = <&tlmm>;
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interrupts = <40 0>;
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spi-max-frequency = <5000000>;
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qcom,clk-freq-mhz = <40000000>;
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qcom,max-can-channels = <1>;
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qcom,bits-per-word = <8>;
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qcom,support-can-fd;
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};
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};
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&soc {
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qcom,lpass@62400000 {
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status = "ok";
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};
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qcom,glink {
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modem {
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status = "disabled";
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};
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};
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ss5_pwr_ctrl0 {
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compatible = "gnss_sirf";
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pinctrl-0 = <&ss5_pwr_ctrl_rst_on>;
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ssVreset-gpio = <&tlmm 87 1>;
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ssVonoff-gpio = <&tlmm 18 1>;
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};
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hsi2s: qcom,hsi2s {
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compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s";
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number-of-interfaces = <2>;
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reg = <0x1B40000 0x28000>;
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reg-names = "lpa_if";
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interrupts = <GIC_SPI 267 0>;
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clocks = <&clock_gcc GCC_SDR_CORE_CLK>,
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<&clock_gcc GCC_SDR_WR0_MEM_CLK>,
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<&clock_gcc GCC_SDR_WR1_MEM_CLK>,
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<&clock_gcc GCC_SDR_WR2_MEM_CLK>,
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<&clock_gcc GCC_SDR_CSR_HCLK>;
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clock-names = "core_clk", "wr0_mem_clk",
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"wr1_mem_clk", "wr2_mem_clk",
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"csr_hclk";
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number-of-rate-detectors = <2>;
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rate-detector-interfaces = <0 1>;
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iommus = <&apps_smmu 0x035C 0x1>;
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qcom,smmu-s1-bypass;
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qcom,iova-mapping = <0x0 0xFFFFFFFF>;
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sdr0: qcom,hs0_i2s {
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compatible = "qcom,hsi2s-interface";
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minor-number = <0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&hs0_i2s_sck_active &hs0_i2s_data0_active
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&hs0_i2s_data1_active>;
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pinctrl-1 = <&hs0_i2s_sck_sleep &hs0_i2s_data0_sleep
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&hs0_i2s_data1_sleep>;
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clocks = <&clock_gcc GCC_SDR_PRI_MI2S_CLK>;
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clock-names = "pri_mi2s_clk";
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bit-clock-hz = <12288000>;
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data-buffer-ms = <10>;
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bit-depth = <32>;
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spkr-channel-count = <2>;
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mic-channel-count = <2>;
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pcm-rate = <2>;
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pcm-sync-src = <0>;
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aux-mode = <0>;
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rpcm-width = <1>;
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tpcm-width = <1>;
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enable-tdm = <1>;
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tdm-rate = <32>;
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tdm-rpcm-width = <16>;
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tdm-tpcm-width = <16>;
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tdm-sync-delay = <2>;
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tdm-inv-sync = <0>;
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pcm-lane-config = <1>;
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};
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sdr1: qcom,hs1_i2s {
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compatible = "qcom,hsi2s-interface";
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minor-number = <1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&hs1_i2s_sck_active &hs1_i2s_data0_active
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&hs1_i2s_data1_active>;
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pinctrl-1 = <&hs1_i2s_sck_sleep &hs1_i2s_data0_sleep
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&hs1_i2s_data1_sleep>;
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clocks = <&clock_gcc GCC_SDR_SEC_MI2S_CLK>;
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clock-names = "sec_mi2s_clk";
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bit-clock-hz = <12288000>;
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data-buffer-ms = <10>;
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bit-depth = <32>;
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spkr-channel-count = <2>;
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mic-channel-count = <2>;
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pcm-rate = <2>;
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pcm-sync-src = <0>;
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aux-mode = <0>;
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rpcm-width = <1>;
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tpcm-width = <1>;
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enable-tdm = <1>;
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tdm-rate = <32>;
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tdm-rpcm-width = <16>;
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tdm-tpcm-width = <16>;
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tdm-sync-delay = <2>;
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tdm-inv-sync = <0>;
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pcm-lane-config = <1>;
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};
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};
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emac_hw: qcom,emac@20000 {
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compatible = "qcom,emac-dwc-eqos";
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qcom,arm-smmu;
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reg = <0x20000 0x10000>,
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<0x36000 0x100>;
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reg-names = "emac-base", "rgmii-base";
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dma-bit-mask = <32>;
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emac-core-version = <7>;
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emac-phy-addr = <7>;
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interrupts-extended = <&pdc 0 660 4>, <&pdc 0 661 4>,
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<&tlmm 121 2>, <&pdc 0 651 4>,
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<&pdc 0 652 4>, <&pdc 0 653 4>,
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<&pdc 0 654 4>, <&pdc 0 655 4>,
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<&pdc 0 656 4>, <&pdc 0 657 4>,
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<&pdc 0 658 4>, <&pdc 0 659 4>,
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<&pdc 0 668 4>, <&pdc 0 669 4>;
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interrupt-names = "sbd-intr", "lpi-intr",
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"phy-intr", "tx-ch0-intr",
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"tx-ch1-intr", "tx-ch2-intr",
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"tx-ch3-intr", "tx-ch4-intr",
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"rx-ch0-intr", "rx-ch1-intr",
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"rx-ch2-intr", "rx-ch3-intr",
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"ptp_pps_irq_0","ptp_pps_irq_1";
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qcom,msm-bus,name = "emac";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<98 512 0 0>, <1 781 0 0>, /* No vote */
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<98 512 1250 0>, <1 781 0 40000>, /* 10Mbps vote */
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<98 512 12500 0>, <1 781 0 40000>, /* 100Mbps vote */
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<98 512 125000 0>, <1 781 0 40000>; /* 1000Mbps vote */
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qcom,bus-vector-names = "0", "10", "100", "1000";
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clocks = <&clock_gcc GCC_EMAC_AXI_CLK>,
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<&clock_gcc GCC_EMAC_PTP_CLK>,
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<&clock_gcc GCC_EMAC_RGMII_CLK>,
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<&clock_gcc GCC_EMAC_SLV_AHB_CLK>;
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clock-names = "eth_axi_clk", "eth_ptp_clk",
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"eth_rgmii_clk", "eth_slave_ahb_clk";
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qcom,phy-reset = <&tlmm 104 GPIO_ACTIVE_HIGH>;
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qcom,phy-reset-delay-msecs = <10 50>;
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qcom,phy-intr-redirect = <&tlmm 121 GPIO_ACTIVE_LOW>;
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gdsc_emac-supply = <&emac_gdsc>;
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pinctrl-names = "dev-emac-mdc", "dev-emac-mdio",
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"dev-emac-rgmii_txd0_state", "dev-emac-rgmii_txd1_state",
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"dev-emac-rgmii_txd2_state", "dev-emac-rgmii_txd3_state",
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"dev-emac-rgmii_txc_state", "dev-emac-rgmii_tx_ctl_state",
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"dev-emac-rgmii_rxd0_state", "dev-emac-rgmii_rxd1_state",
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"dev-emac-rgmii_rxd2_state", "dev-emac-rgmii_rxd3_state",
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"dev-emac-rgmii_rxc_state", "dev-emac-rgmii_rx_ctl_state",
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"dev-emac-phy_intr", "dev-emac-phy_reset_state",
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"dev-emac_pin_pps_0", "dev-emac-rgmii_rxc_suspend_state",
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"dev-emac-rgmii_rxc_resume_state";
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pinctrl-0 = <&emac_mdc>;
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pinctrl-1 = <&emac_mdio>;
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pinctrl-2 = <&emac_rgmii_txd0>;
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pinctrl-3 = <&emac_rgmii_txd1>;
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pinctrl-4 = <&emac_rgmii_txd2>;
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pinctrl-5 = <&emac_rgmii_txd3>;
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pinctrl-6 = <&emac_rgmii_txc>;
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pinctrl-7 = <&emac_rgmii_tx_ctl>;
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pinctrl-8 = <&emac_rgmii_rxd0>;
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pinctrl-9 = <&emac_rgmii_rxd1>;
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pinctrl-10 = <&emac_rgmii_rxd2>;
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pinctrl-11 = <&emac_rgmii_rxd3>;
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pinctrl-12 = <&emac_rgmii_rxc>;
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pinctrl-13 = <&emac_rgmii_rx_ctl>;
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pinctrl-14 = <&emac_phy_intr>;
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pinctrl-15 = <&emac_phy_reset_state>;
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pinctrl-16 = <&emac_pin_pps_0>;
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pinctrl-17 = <&emac_rgmii_rxc_suspend>;
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pinctrl-18 = <&emac_rgmii_rxc_resume>;
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io-macro-info {
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io-macro-bypass-mode = <0>;
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io-interface = "rgmii";
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};
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emac_emb_smmu: emac_emb_smmu {
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compatible = "qcom,emac-smmu-embedded";
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iommus = <&apps_smmu 0x1C0 0x0>;
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qcom,iova-mapping = <0x80000000 0x40000000>;
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};
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};
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};
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qmp-v3-660";
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vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */
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vdda-pll-supply = <&pm6155_1_l12>;
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vdda-phy-max-microamp = <30000>;
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vdda-pll-max-microamp = <12000>;
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status = "ok";
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};
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&ufshc_mem {
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vdd-hba-supply = <&ufs_phy_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm6155_1_l17>;
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vcc-voltage-level = <2950000 2960000>;
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vccq2-supply = <&pm6155_1_s4>;
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vcc-max-microamp = <800000>;
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vccq2-max-microamp = <600000>;
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qcom,vddp-ref-clk-supply = <&pm6155_1_l11>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vddp-ref-clk-min-uV = <1232000>;
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qcom,vddp-ref-clk-max-uV = <1260000>;
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status = "ok";
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};
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&sdhc_1 {
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vdd-supply = <&pm6155_1_l17>;
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qcom,vdd-voltage-level = <2950000 2950000>;
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qcom,vdd-current-level = <0 570000>;
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vdd-io-supply = <&pm6155_1_s4>;
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qcom,vdd-io-always-on;
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qcom,vdd-io-lpm-sup;
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qcom,vdd-io-voltage-level = <1800000 1800000>;
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qcom,vdd-io-current-level = <0 325000>;
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pinctrl-names = "active", "sleep";
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pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
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pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
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qcom,restore-after-cx-collapse;
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status = "ok";
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};
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&sdhc_2 {
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vdd-supply = <&pm6155_1_l10>;
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qcom,vdd-voltage-level = <2950000 2950000>;
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qcom,vdd-current-level = <0 800000>;
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vdd-io-supply = <&pm6155_1_l2>;
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qcom,vdd-io-voltage-level = <1800000 3100000>;
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qcom,vdd-io-current-level = <0 22000>;
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pinctrl-names = "active", "sleep";
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pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
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pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
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cd-gpios = <&tlmm 99 1>;
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qcom,restore-after-cx-collapse;
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status = "ok";
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};
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&usb0 {
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qcom,ignore-wakeup-src-in-hostmode;
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};
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&usb1 {
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status = "ok";
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qcom,default-mode-host;
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qcom,ignore-wakeup-src-in-hostmode;
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};
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&qupv3_se0_2uart {
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status = "ok";
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};
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&qupv3_se4_2uart {
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status = "ok";
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};
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&qupv3_se7_4uart {
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status = "ok";
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};
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