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216 lines
5.8 KiB
216 lines
5.8 KiB
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/qcom,gcc-qcs405.h>
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#include <dt-bindings/msm/msm-bus-ids.h>
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&soc {
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/* Secondary USB port related controller */
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usb3: ssusb@7580000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x7580000 0x100000>;
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reg-names = "core_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <0 25 0>, <0 319 0>;
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interrupt-names = "pwr_event_irq", "hs_phy_irq";
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dpdm-supply = <&usb2_phy0>;
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clocks = <&clock_gcc GCC_USB30_MASTER_CLK>,
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<&clock_gcc GCC_SYS_NOC_USB3_CLK>,
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<&clock_gcc GCC_USB30_SLEEP_CLK>,
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<&clock_gcc GCC_USB30_MOCK_UTMI_CLK>,
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<&clock_rpmcc CXO_SMD_OTG_CLK>,
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<&clock_gcc GCC_PCNOC_USB3_CLK>;
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clock-names = "core_clk", "iface_clk", "sleep_clk",
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"utmi_clk", "xo", "noc_aggr_clk";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <100000000>;
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qcom,pm-qos-latency = <181>;
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qcom,msm-bus,name = "usb3";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<MSM_BUS_MASTER_USB3
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MSM_BUS_SLAVE_EBI_CH0 0 0>,
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<MSM_BUS_MASTER_USB3
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MSM_BUS_SLAVE_EBI_CH0 240000 700000>;
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resets = <&clock_gcc GCC_USB_30_BCR>;
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reset-names = "core_reset";
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dwc3@7580000 {
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compatible = "snps,dwc3";
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reg = <0x7580000 0xcd00>;
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interrupts = <0 26 0>;
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usb-phy = <&usb2_phy1>, <&usb_ss_phy>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3-u1u2-disable;
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usb-core-id = <1>;
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maximum-speed = "super-speed";
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dr_mode = "host";
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};
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};
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/* Secondary USB port related High Speed PHY */
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usb2_phy1: hsphy@7a000 {
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compatible = "qcom,usb-snps-hsphy";
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reg = <0x7a000 0x200>;
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reg-names = "phy_csr";
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vdd-supply = <&pms405_l4>;
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vdda18-supply = <&pms405_l5>;
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vdda33-supply = <&pms405_l12>;
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qcom,vdd-voltage-level = <0 1144000 1200000>;
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clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK>,
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<&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
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<&clock_gcc GCC_USB2A_PHY_SLEEP_CLK>;
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clock-names = "ref_clk", "phy_csr_clk", "sleep_clk";
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resets = <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
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<&clock_gcc GCC_USB2A_PHY_BCR>;
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reset-names = "phy_reset", "phy_por_reset";
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qcom,snps-hs-phy-init-seq =
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<0xc0 0x01 0>,
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<0xe8 0x0d 0>,
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<0x74 0x12 0>,
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<0x98 0x63 0>,
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<0x9c 0x03 0>,
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<0xa0 0x1d 0>,
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<0xa4 0x03 0>,
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<0x8c 0x23 0>,
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<0x78 0x08 0>,
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<0x7c 0xdc 0>,
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<0x90 0xe0 20>,
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<0x74 0x10 0>,
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<0x90 0x60 0>,
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<0xffffffff 0xffffffff 0>;
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};
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/* Secondary USB port related Super Speed PHY */
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usb_ss_phy: ssphy@78000 {
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compatible = "qcom,usb-ssphy";
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reg = <0x78000 0x400>;
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vdd-supply = <&pms405_l3>;
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vdda18-supply = <&pms405_l5>;
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qcom,vdd-voltage-level = <0 1050000 1050000>;
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clocks = <&clock_cmn_blk_pll CMN_BLK_PLL>,
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<&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
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<&clock_gcc GCC_USB3_PHY_PIPE_CLK>;
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clock-names = "ref_clk", "cfg_ahb_clk", "pipe_clk";
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resets = <&clock_gcc GCC_USB3_PHY_BCR>,
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<&clock_gcc GCC_USB3PHY_PHY_BCR>;
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reset-names = "phy_reset", "phy_com_reset";
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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/* Primary USB port related controller */
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usb2s: hsusb@78c0000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x78c0000 0x100000>;
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reg-names = "core_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <0 32 0>, <0 318 0>;
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interrupt-names = "pwr_event_irq", "hs_phy_irq";
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clocks = <&clock_gcc GCC_USB_HS_SYSTEM_CLK>,
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<&clock_gcc GCC_PCNOC_USB2_CLK>,
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<&clock_gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
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<&clock_gcc GCC_USB20_MOCK_UTMI_CLK>,
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<&clock_rpmcc CXO_SMD_OTG_CLK>;
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clock-names = "core_clk", "iface_clk", "sleep_clk",
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"utmi_clk", "xo";
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qcom,core-clk-rate = <133333333>;
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qcom,msm-bus,name = "usb2s";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<MSM_BUS_MASTER_USB_HS
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MSM_BUS_SLAVE_EBI_CH0 0 0>,
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<MSM_BUS_MASTER_USB_HS
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MSM_BUS_SLAVE_EBI_CH0 60000 800000>;
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resets = <&clock_gcc GCC_USB_HS_BCR>;
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reset-names = "core_reset";
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dwc3@78c0000 {
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compatible = "snps,dwc3";
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reg = <0x78c0000 0xcd00>;
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interrupts = <0 44 0>;
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usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3_lpm_capable;
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usb-core-id = <0>;
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maximum-speed = "high-speed";
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dr_mode = "otg";
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};
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};
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/* Primary USB port related High Speed PHY */
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usb2_phy0: hsphy@7c000 {
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compatible = "qcom,usb-snps-hsphy";
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reg = <0x7c000 0x200>;
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reg-names = "phy_csr";
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vdd-supply = <&pms405_l4>;
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vdda18-supply = <&pms405_l5>;
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vdda33-supply = <&pms405_l12>;
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qcom,vdd-voltage-level = <0 1144000 1200000>;
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clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK>,
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<&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
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<&clock_gcc GCC_USB2A_PHY_SLEEP_CLK>;
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clock-names = "ref_clk", "phy_csr_clk", "sleep_clk";
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resets = <&clock_gcc GCC_QUSB2_PHY_BCR>,
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<&clock_gcc GCC_USB2_HS_PHY_ONLY_BCR>;
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reset-names = "phy_reset", "phy_por_reset";
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qcom,snps-hs-phy-init-seq =
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<0xc0 0x01 0>,
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<0xe8 0x0d 0>,
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<0x74 0x12 0>,
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<0x98 0x63 0>,
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<0x9c 0x03 0>,
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<0xa0 0x1d 0>,
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<0xa4 0x03 0>,
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<0x8c 0x23 0>,
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<0x78 0x08 0>,
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<0x7c 0xdc 0>,
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<0x90 0xe0 20>,
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<0x74 0x10 0>,
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<0x90 0x60 0>,
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<0xffffffff 0xffffffff 0>;
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};
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};
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