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126 lines
3.1 KiB
126 lines
3.1 KiB
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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mdss_dsi0_pll: qcom,mdss_dsi_pll@1a94a00 {
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compatible = "qcom,mdss_dsi_pll_28lpm";
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label = "MDSS DSI 0 PLL";
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cell-index = <0>;
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#clock-cells = <1>;
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reg = <0x01a94a00 0xd4>,
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<0x0184d074 0x8>;
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reg-names = "pll_base", "gdsc_base";
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clocks = <&clock_gcc GCC_MDSS_AHB_CLK>;
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clock-names = "iface_clk";
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clock-rate = <0>;
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gdsc-supply = <&gdsc_mdss>;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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qcom,ssc-frequency-hz = <30000>;
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qcom,ssc-ppm = <5000>;
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "gdsc";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_dsi1_pll: qcom,mdss_dsi_pll@1a96a00 {
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status="disabled";
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compatible = "qcom,mdss_dsi_pll_28lpm";
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label = "MDSS DSI 1 PLL";
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cell-index = <1>;
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#clock-cells = <1>;
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reg = <0x01a96a00 0xd4>,
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<0x0184d074 0x8>;
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reg-names = "pll_base", "gdsc_base";
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clocks = <&clock_gcc GCC_MDSS_AHB_CLK>;
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clock-names = "iface_clk";
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clock-rate = <0>;
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gdsc-supply = <&gdsc_mdss>;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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qcom,ssc-frequency-hz = <30000>;
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qcom,ssc-ppm = <5000>;
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "gdsc";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_hdmi_pll: qcom,mdss_hdmi_pll@0x1aa0600 {
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compatible = "qcom,mdss_hdmi_pll_28lpm";
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label = "MDSS HDMI PLL";
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cell-index = <0>;
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#clock-cells = <1>;
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reg = <0x1aa0600 0x49c>,
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<0x0184d074 0x8>;
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reg-names = "pll_base", "gdsc_base";
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gdsc-supply = <&gdsc_mdss>;
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vddx-pll-supply = <&pms405_l5>;
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clocks = <&clock_gcc GCC_MDSS_AHB_CLK>;
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clock-names = "iface_clk";
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clock-rate = <0>;
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "gdsc";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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qcom,platform-supply-entry@1 {
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reg = <1>;
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qcom,supply-name = "vddx-pll";
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qcom,supply-min-voltage = <1800000>;
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qcom,supply-max-voltage = <1800000>;
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qcom,supply-enable-load = <14300>;
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qcom,supply-disable-load = <1>;
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};
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};
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};
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};
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