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187 lines
5.0 KiB
187 lines
5.0 KiB
/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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msm_bus: qcom,kgsl-busmon {
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label = "kgsl-busmon";
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compatible = "qcom,kgsl-busmon";
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};
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gpu_bw_tbl: gpu-bw-tbl {
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compatible = "operating-points-v2";
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opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */
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opp-100 { opp-hz = /bits/ 64 < 769 >; }; /* 1. DDR:100.80MHz */
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opp-211 { opp-hz = /bits/ 64 < 1611 >; }; /* 2. DDR:211.20MHz */
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opp-297 { opp-hz = /bits/ 64 < 2270 >; }; /* 3. DDR:297.60MHz */
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opp-384 { opp-hz = /bits/ 64 < 2929 >; }; /* 4. DDR:384.00MHz */
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opp-556 { opp-hz = /bits/ 64 < 4248 >; }; /* 5. DDR:556.80MHz */
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opp-595 { opp-hz = /bits/ 64 < 4541 >; }; /* 6. DDR:595.20MHz */
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opp-672 { opp-hz = /bits/ 64 < 5126 >; }; /* 7. DDR:672.00MHz */
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opp-740 { opp-hz = /bits/ 64 < 5639 >; }; /* 8. DDR:739.20MHz */
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};
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/* Bus governor */
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gpubw: qcom,gpubw {
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compatible = "qcom,devbw";
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governor = "bw_vbif";
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qcom,src-dst-ports = <26 512>;
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operating-points-v2 = <&gpu_bw_tbl>;
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};
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msm_gpu: qcom,kgsl-3d0@1c00000 {
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label = "kgsl-3d0";
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compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
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reg = <0x1c00000 0x10000
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0x1c10000 0x10000
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0x00a0000 0x06fff>;
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reg-names = "kgsl_3d0_reg_memory", "kgsl_3d0_shader_memory",
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"qfprom_memory";
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interrupts = <0 33 0>;
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interrupt-names = "kgsl_3d0_irq";
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qcom,id = <0>;
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qcom,chipid = <0x03000620>;
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qcom,initial-pwrlevel = <3>;
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qcom,idle-timeout = <80>; //msecs
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qcom,strtstp-sleepwake;
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qcom,gpu-bimc-interface-clk-freq = <400000000>; //In Hz
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qcom,gpu-disable-fuse = <0x41a0 0x00000001 29>;
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clocks = <&clock_gcc GCC_OXILI_GFX3D_CLK>,
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<&clock_gcc GCC_OXILI_AHB_CLK>,
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<&clock_gcc GCC_BIMC_GFX_CLK>,
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<&clock_gcc GCC_BIMC_GPU_CLK>,
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<&clock_gcc GCC_GTCU_AHB_CLK>,
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<&clock_gcc GCC_GFX_TCU_CLK>,
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<&clock_gcc GCC_GFX_TBU_CLK>,
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<&clock_rpmcc RPM_SMD_BIMC_GPU_CLK>;
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clock-names = "core_clk", "iface_clk", "mem_iface_clk",
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"alt_mem_iface_clk", "gtcu_iface_clk",
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"gtcu_clk", "gtbu_clk", "bimc_gpu_clk";
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/* Bus Scale Settings */
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qcom,gpubw-dev = <&gpubw>;
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qcom,bus-control;
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qcom,bus-width = <16>;
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qcom,msm-bus,name = "grp3d";
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qcom,msm-bus,num-cases = <9>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<26 512 0 0>, /* off */
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<26 512 0 806400>, /* 1. 100.80 MHz */
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<26 512 0 1689600>, /* 2. 211.20 MHz */
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<26 512 0 2380800>, /* 3. 297.60 MHz */
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<26 512 0 3072000>, /* 4. 384.00 MHz */
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<26 512 0 4454400>, /* 5. 556.80 MHz */
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<26 512 0 4761600>, /* 6. 595.20 MHz */
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<26 512 0 5376000>, /* 7. 672.00 MHz */
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<26 512 0 5913600>; /* 8. 739.20 MHz */
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/* GDSC regulator names */
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regulator-names = "vdd";
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/* GDSC oxili regulators */
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vdd-supply = <&gdsc_oxili_gx>;
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/* CPU latency parameter */
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qcom,pm-qos-active-latency = <651>;
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/* Enable gpu cooling device */
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#cooling-cells = <2>;
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/* Power levels */
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qcom,gpu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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/* TURBO */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <598000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <8>;
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};
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/* NOM+ */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <523200000>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <5>;
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qcom,bus-max = <7>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <484800000>;
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qcom,bus-freq = <5>;
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qcom,bus-min = <4>;
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qcom,bus-max = <6>;
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};
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/* SVS+ */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <400000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <270000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <1>;
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qcom,bus-max = <3>;
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};
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/* XO */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <19200000>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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};
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kgsl_msm_iommu: qcom,kgsl-iommu@1f00000 {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x1f00000 0x10000>;
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/*
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* The gpu can only program a single context bank
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* at this fixed offset.
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*/
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qcom,protect = <0xa000 0x1000>;
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clocks = <&clock_gcc GCC_SMMU_CFG_CLK>,
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<&clock_gcc GCC_GFX_TCU_CLK>,
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<&clock_gcc GCC_GTCU_AHB_CLK>,
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<&clock_gcc GCC_GFX_TBU_CLK>;
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clock-names = "scfg_clk", "gtcu_clk", "gtcu_iface_clk",
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"gtbu_clk";
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qcom,retention;
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&gfx_iommu 0>;
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qcom,gpu-offset = <0xa000>;
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};
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};
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};
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