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172 lines
3.9 KiB
172 lines
3.9 KiB
/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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msm_npu: qcom,msm_npu@9800000 {
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compatible = "qcom,msm-npu";
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status = "ok";
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reg = <0x9900000 0x20000>,
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<0x99f0000 0x10000>,
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<0x9980000 0x10000>,
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<0x17c00000 0x10000>,
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<0x01f40000 0x40000>,
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<0x780000 0x7000>;
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reg-names = "tcm", "core", "cc", "apss_shared", "tcsr",
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"qfprom_physical";
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interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 588 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",
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"general_irq";
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iommus = <&apps_smmu 0x1441 0x0>, <&apps_smmu 0x1442 0x0>,
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<&apps_smmu 0x1461 0x0>, <&apps_smmu 0x1462 0x0>,
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<&apps_smmu 0x1481 0x0>, <&apps_smmu 0x1482 0x0>;
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qcom,npu-dsp-sid-mapped;
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clocks = <&clock_npucc NPU_CC_XO_CLK>,
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<&clock_npucc NPU_CC_CORE_CLK>,
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<&clock_npucc NPU_CC_CAL_HM0_CLK>,
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<&clock_npucc NPU_CC_CAL_HM0_CDC_CLK>,
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<&clock_npucc NPU_CC_NOC_AXI_CLK>,
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<&clock_npucc NPU_CC_NOC_AHB_CLK>,
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<&clock_npucc NPU_CC_NOC_DMA_CLK>,
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<&clock_npucc NPU_CC_RSC_XO_CLK>,
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<&clock_npucc NPU_CC_S2P_CLK>,
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<&clock_npucc NPU_CC_BWMON_CLK>,
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<&clock_npucc NPU_CC_CAL_HM0_PERF_CNT_CLK>,
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<&clock_npucc NPU_CC_BTO_CORE_CLK>,
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<&clock_npucc NPU_DSP_CORE_CLK_SRC>;
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clock-names = "xo_clk",
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"npu_core_clk",
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"cal_hm0_clk",
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"cal_hm0_cdc_clk",
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"axi_clk",
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"ahb_clk",
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"dma_clk",
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"rsc_xo_clk",
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"s2p_clk",
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"bwmon_clk",
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"cal_hm0_perf_cnt_clk",
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"bto_core_clk",
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"dsp_core_clk_src";
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vdd-supply = <&npu_core_gdsc>;
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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qcom,proxy-reg-names ="vdd", "vdd_cx";
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qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
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#cooling-cells = <2>;
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mboxes = <&apcs_glb2 4>,
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<&apcs_glb2 6>;
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mbox-names = "glink", "smp2p";
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#mbox-cells = <1>;
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qcom,npubw-devs = <&npu_npu_ddr_bw>, <&npudsp_npu_ddr_bw>;
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qcom,npubw-dev-names = "ddr_bw", "dsp_ddr_bw";
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qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>,
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<MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_CLK_CTL>;
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qcom,npu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,npu-pwrlevels";
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initial-pwrlevel = <4>;
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qcom,npu-pwrlevel@0 {
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reg = <0>;
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vreg = <1>;
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clk-freq = <19200000
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100000000
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192000000
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192000000
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150000000
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30000000
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200000000
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19200000
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50000000
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19200000
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192000000
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19200000
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300000000>;
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};
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qcom,npu-pwrlevel@1 {
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reg = <1>;
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vreg = <2>;
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clk-freq = <19200000
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200000000
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268800000
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268800000
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200000000
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37500000
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300000000
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19200000
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50000000
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19200000
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268800000
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19200000
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400000000>;
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};
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qcom,npu-pwrlevel@2 {
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reg = <2>;
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vreg = <3>;
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clk-freq = <19200000
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333000000
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403200000
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403200000
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300000000
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37500000
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403000000
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19200000
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50000000
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19200000
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403200000
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19200000
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500000000>;
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};
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qcom,npu-pwrlevel@3 {
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reg = <3>;
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vreg = <4>;
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clk-freq = <19200000
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428000000
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515000000
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515000000
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403000000
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75000000
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600000000
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19200000
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100000000
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19200000
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515000000
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19200000
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660000000>;
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};
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qcom,npu-pwrlevel@4 {
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reg = <4>;
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vreg = <6>;
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clk-freq = <19200000
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500000000
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748800000
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748800000
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533000000
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75000000
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710000000
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19200000
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100000000
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19200000
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748800000
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19200000
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800000000>;
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};
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};
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};
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};
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