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214 lines
4.7 KiB
214 lines
4.7 KiB
/*
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* Device Tree Include file for Freescale Layerscape-1043A family SoC.
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*
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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*
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* Mingkai Hu <Mingkai.hu@freescale.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPLv2 or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "fsl-ls1043a.dtsi"
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/ {
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model = "LS1043A RDB Board";
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aliases {
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crypto = &crypto;
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serial0 = &duart0;
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serial1 = &duart1;
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serial2 = &duart2;
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serial3 = &duart3;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&i2c0 {
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status = "okay";
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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adt7461a@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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eeprom@52 {
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compatible = "atmel,24c512";
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reg = <0x52>;
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};
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eeprom@53 {
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compatible = "atmel,24c512";
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reg = <0x53>;
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};
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rtc@68 {
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compatible = "pericom,pt7c4338";
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reg = <0x68>;
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};
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};
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&ifc {
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status = "okay";
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR, NAND Flashes and FPGA on board */
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ranges = <0x0 0x0 0x0 0x60000000 0x08000000
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0x1 0x0 0x0 0x7e800000 0x00010000
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0x2 0x0 0x0 0x7fb00000 0x00000100>;
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nor@0,0 {
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compatible = "cfi-flash";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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nand@1,0 {
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compatible = "fsl,ifc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x1 0x0 0x10000>;
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};
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cpld: board-control@2,0 {
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compatible = "fsl,ls1043ardb-cpld";
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reg = <0x2 0x0 0x0000100>;
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};
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};
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&dspi0 {
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bus-num = <0>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
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reg = <0>;
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spi-max-frequency = <1000000>; /* input clock */
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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#include "fsl-ls1043-post.dtsi"
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&fman0 {
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ethernet@e0000 {
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phy-handle = <&qsgmii_phy1>;
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phy-connection-type = "qsgmii";
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};
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ethernet@e2000 {
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phy-handle = <&qsgmii_phy2>;
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phy-connection-type = "qsgmii";
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};
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ethernet@e4000 {
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii-id";
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};
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ethernet@e6000 {
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phy-handle = <&rgmii_phy2>;
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phy-connection-type = "rgmii-id";
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};
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ethernet@e8000 {
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phy-handle = <&qsgmii_phy3>;
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phy-connection-type = "qsgmii";
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};
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ethernet@ea000 {
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phy-handle = <&qsgmii_phy4>;
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phy-connection-type = "qsgmii";
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};
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ethernet@f0000 { /* 10GEC1 */
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phy-handle = <&aqr105_phy>;
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phy-connection-type = "xgmii";
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};
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mdio@fc000 {
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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qsgmii_phy1: ethernet-phy@4 {
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reg = <0x4>;
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};
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qsgmii_phy2: ethernet-phy@5 {
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reg = <0x5>;
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};
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qsgmii_phy3: ethernet-phy@6 {
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reg = <0x6>;
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};
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qsgmii_phy4: ethernet-phy@7 {
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reg = <0x7>;
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};
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};
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mdio@fd000 {
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aqr105_phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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interrupts = <0 132 4>;
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reg = <0x1>;
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};
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};
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};
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