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178 lines
4.2 KiB
178 lines
4.2 KiB
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_ARM_FUTEX_H
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#define _ASM_ARM_FUTEX_H
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#ifdef __KERNEL__
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/errno.h>
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#define __futex_atomic_ex_table(err_reg) \
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"3:\n" \
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" .pushsection __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 1b, 4f, 2b, 4f\n" \
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" .popsection\n" \
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" .pushsection .text.fixup,\"ax\"\n" \
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" .align 2\n" \
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"4: mov %0, " err_reg "\n" \
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" b 3b\n" \
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" .popsection"
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#ifdef CONFIG_SMP
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#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
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({ \
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unsigned int __ua_flags; \
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smp_mb(); \
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prefetchw(uaddr); \
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__ua_flags = uaccess_save_and_enable(); \
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__asm__ __volatile__( \
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"1: ldrex %1, [%3]\n" \
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" " insn "\n" \
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"2: strex %2, %0, [%3]\n" \
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" teq %2, #0\n" \
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" bne 1b\n" \
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" mov %0, #0\n" \
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__futex_atomic_ex_table("%5") \
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: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
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: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
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: "cc", "memory"); \
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uaccess_restore(__ua_flags); \
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})
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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u32 oldval, u32 newval)
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{
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unsigned int __ua_flags;
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int ret;
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u32 val;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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return -EFAULT;
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smp_mb();
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/* Prefetching cannot fault */
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prefetchw(uaddr);
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__ua_flags = uaccess_save_and_enable();
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__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
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"1: ldrex %1, [%4]\n"
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" teq %1, %2\n"
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" ite eq @ explicit IT needed for the 2b label\n"
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"2: strexeq %0, %3, [%4]\n"
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" movne %0, #0\n"
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" teq %0, #0\n"
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" bne 1b\n"
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__futex_atomic_ex_table("%5")
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: "=&r" (ret), "=&r" (val)
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: "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
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: "cc", "memory");
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uaccess_restore(__ua_flags);
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smp_mb();
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*uval = val;
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return ret;
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}
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#else /* !SMP, we can work around lack of atomic ops by disabling preemption */
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#include <linux/preempt.h>
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#include <asm/domain.h>
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#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
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({ \
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unsigned int __ua_flags = uaccess_save_and_enable(); \
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__asm__ __volatile__( \
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"1: " TUSER(ldr) " %1, [%3]\n" \
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" " insn "\n" \
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"2: " TUSER(str) " %0, [%3]\n" \
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" mov %0, #0\n" \
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__futex_atomic_ex_table("%5") \
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: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
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: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
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: "cc", "memory"); \
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uaccess_restore(__ua_flags); \
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})
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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u32 oldval, u32 newval)
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{
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unsigned int __ua_flags;
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int ret = 0;
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u32 val;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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return -EFAULT;
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preempt_disable();
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__ua_flags = uaccess_save_and_enable();
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__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
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"1: " TUSER(ldr) " %1, [%4]\n"
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" teq %1, %2\n"
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" it eq @ explicit IT needed for the 2b label\n"
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"2: " TUSER(streq) " %3, [%4]\n"
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__futex_atomic_ex_table("%5")
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: "+r" (ret), "=&r" (val)
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: "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
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: "cc", "memory");
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uaccess_restore(__ua_flags);
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*uval = val;
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preempt_enable();
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return ret;
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}
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#endif /* !SMP */
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static inline int
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arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
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{
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int oldval = 0, ret, tmp;
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#ifndef CONFIG_SMP
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preempt_disable();
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#endif
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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#ifndef CONFIG_SMP
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preempt_enable();
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#endif
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/*
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* Store unconditionally. If ret != 0 the extra store is the least
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* of the worries but GCC cannot figure out that __futex_atomic_op()
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* is either setting ret to -EFAULT or storing the old value in
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* oldval which results in a uninitialized warning at the call site.
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*/
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*oval = oldval;
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return ret;
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_ARM_FUTEX_H */
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