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189 lines
5.9 KiB
189 lines
5.9 KiB
Qualcomm Technologies, Inc. High Speed I2S Interface
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* HS-I2S generic node
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Required properties:
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- compatible : Should include "qcom,hsi2s"
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Should include target specific compatible field
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"qcom,sa6155-hsi2s" for SA6155
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"qcom,sa8155-hsi2s" for SA8155
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"qcom,sa8195-hsi2s" for SA8195
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- number-of-interfaces : Denotes the number of HS-I2S interfaces
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- reg : Specifies the base physical address and the size of the HS-I2S
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register space
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- reg-names : "lpa_if" - string to identify the HS-I2S base register
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- interrupts : Interrupt number used by this interface
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- clocks : Core clocks used by this interface
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- clock-names : Clock names for each core clock
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- iommus: The phandle and stream IDs for the SMMU used by this root
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- qcom,iova-mapping: Specifies the start address and size of iova space
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Optional properties:
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- number-of-rate-detectors : Number of rate detectors to enable
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0 - Doesn't enable rate detectors
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1 - Enables primary rate detector
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2 - Enables both primary and secondary
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rate detectors
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- rate-detector-interfaces : Specifies the minor number of the interfaces
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to have rate detection enabled
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- qcom,smmu-s1-bypass: Boolean, if present S1 bypass is enabled
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* HS-I2S interface nodes
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Required properties:
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- compatible : Should be "qcom,hsi2s-interface"
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- minor-number : Minor number of the character device interface
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Should be 0 for HS0 interface
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Should be 1 for HS1 interface
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Should be 2 for HS2 interface
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- clocks : Interface clock used by this interface
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- clock-names : Clock name for the interface clock
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- pinctrl-names : Pinctrl state names for each pin group configuration
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- pinctrl-x : Defines pinctrl state for each pin group
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- bit-clock-hz : Default bit clock frequency in hertz
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- data-buffer-ms : Default periodic interrupt interval in milliseconds
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Optional properties:
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- bit-depth : Bit depth of the I2S data
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Default - 32
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- spkr-channel-count : Number of speaker channels
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Default - 2
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- mic-channel-count : Number of mic channels
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Default - 2
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- pcm-rate : Number of bit clocks per PCM frame
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0 - ENUM_8
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1 - ENUM_16
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2 - ENUM_32 (Default)
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3 - ENUM_64
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4 - ENUM_128
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5 - ENUM_256
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- pcm-sync-src : Specifies whether the PCM block uses internal or
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external sync
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0 - External (Default)
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1 - Internal
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- aux-mode : Specifies the type of sync expected/generated by the
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PCM block.
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0 - PCM (Short sync) (Default)
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1 - Aux PCM (Long sync)
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- rpcm-width : Number of bits per receive slot
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0 - 8 bits
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1 - 16 bits (Default)
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- tpcm-width : Number of bits per transmit slot
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0 - 8 bits
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1 - 16 bits (Default)
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- enable-tdm : Specifies whether TDM is enabled by default
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0 - Disable TDM
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1 - Enable TDM (Default)
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- tdm-rate : Number of bit clocks per TDM frame
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Maximum permissible value is 512
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Default - 32
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- tdm-rpcm-width : Number of bits per receive slot in TDM
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Maximum permissible value is 32
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Default - 16
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- tdm-tpcm-width : Number of bits per transmit slot in TDM
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Maximum permissible value is 32
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Default - 16
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- tdm-sync-delay : Specifies the data delay relative to sync pulse
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0 - First data appears two cycles after frame pulse
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1 - First data appears one cycle after frame pulse
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2 - First data and frame pulse occur on the same cycle
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Default - 2
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- tdm-inv-sync : Specifies whether the frame sync has to be inverted
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in long sync(Aux PCM) mode
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0 - Do not invert frame sync (Default)
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1 - Invert frame sync
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- pcm-lane-config : Specifies the PCM data lane configuration
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0 - Single lane
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D0 - MIC
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D1 - SPEAKER
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1 - Multi lane Rx (Default)
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D0 - MIC
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D1 - MIC
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2 - Multi lane Tx
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D0 - SPEAKER
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D1 - SPEAKER
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Example:
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hsi2s: qcom,hsi2s {
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compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s";
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number-of-interfaces = <2>;
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reg = <0x1B40000 0x28000>;
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reg-names = "lpa_if";
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interrupts = <GIC_SPI 267 0>;
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clocks = <&clock_gcc GCC_SDR_CORE_CLK>,
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<&clock_gcc GCC_SDR_WR0_MEM_CLK>,
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<&clock_gcc GCC_SDR_WR1_MEM_CLK>,
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<&clock_gcc GCC_SDR_WR2_MEM_CLK>,
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<&clock_gcc GCC_SDR_CSR_HCLK>;
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clock-names = "core_clk", "wr0_mem_clk",
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"wr1_mem_clk", "wr2_mem_clk",
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"csr_hclk";
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number-of-rate-detectors = <2>;
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rate-detector-interfaces = <0 1>;
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iommus = <&apps_smmu 0x035C 0x1>;
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qcom,smmu-s1-bypass;
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qcom,iova-mapping = <0x0 0xFFFFFFFF>;
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sdr0: qcom,hs0_i2s {
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compatible = "qcom,hsi2s-interface";
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minor-number = <0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&hs0_i2s_sck_active &hs0_i2s_data0_active
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&hs0_i2s_data1_active>;
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pinctrl-1 = <&hs0_i2s_sck_sleep &hs0_i2s_data0_sleep
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&hs0_i2s_data1_sleep>;
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clocks = <&clock_gcc GCC_SDR_PRI_MI2S_CLK>;
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clock-names = "pri_mi2s_clk";
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bit-clock-hz = <12288000>;
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data-buffer-ms = <10>;
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bit-depth = <32>;
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spkr-channel-count = <2>;
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mic-channel-count = <2>;
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pcm-rate = <2>;
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pcm-sync-src = <0>;
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aux-mode = <0>;
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rpcm-width = <1>;
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tpcm-width = <1>;
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enable-tdm = <1>;
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tdm-rate = <32>;
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tdm-rpcm-width = <16>;
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tdm-tpcm-width = <16>;
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tdm-sync-delay = <2>;
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tdm-inv-sync = <0>;
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pcm-lane-config = <1>;
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};
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sdr1: qcom,hs1_i2s {
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compatible = "qcom,hsi2s-interface";
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minor-number = <1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&hs1_i2s_sck_active &hs1_i2s_data0_active
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&hs1_i2s_data1_active>;
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pinctrl-1 = <&hs1_i2s_sck_sleep &hs1_i2s_data0_sleep
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&hs1_i2s_data1_sleep>;
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clocks = <&clock_gcc GCC_SDR_SEC_MI2S_CLK>;
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clock-names = "sec_mi2s_clk";
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bit-clock-hz = <12288000>;
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data-buffer-ms = <10>;
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bit-depth = <32>;
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spkr-channel-count = <2>;
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mic-channel-count = <2>;
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pcm-rate = <2>;
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pcm-sync-src = <0>;
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aux-mode = <0>;
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rpcm-width = <1>;
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tpcm-width = <1>;
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enable-tdm = <1>;
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tdm-rate = <32>;
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tdm-rpcm-width = <16>;
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tdm-tpcm-width = <16>;
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tdm-sync-delay = <2>;
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tdm-inv-sync = <0>;
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pcm-lane-config = <1>;
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};
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};
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