/* * Copyright (c) 2018-2019, The Linux Foundation.All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include "skeleton64.dtsi" #include #include #include #include #include #include #include #include #include #include #include #define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) #define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} #define DDR_TYPE_LPDDR3 5 #define DDR_TYPE_LPDDR4X 7 / { model = "Qualcomm Technologies, Inc. TRINKET"; compatible = "qcom,trinket"; qcom,msm-id = <394 0x10000>; qcom,msm-name = "trinket"; qcom,pmic-name = "pm6125 + pmi632"; interrupt-parent = <&wakegic>; mem-offline { compatible = "qcom,mem-offline"; offline-sizes = <0x1 0x40000000 0x0 0x80000000>, <0x1 0xc0000000 0x0 0xc0000000>, <0x2 0xc0000000 0x1 0x40000000>; granule = <512>; }; aliases { serial0 = &qupv3_se4_2uart; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ ufshc1 = &ufshc_mem; /* Embedded UFS slot */ swr0 = &swr0; swr1 = &swr1; swr2 = &swr2; }; cpus { #address-cells = <2>; #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; }; L1_I_0: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9040>; }; L1_D_0: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9040>; }; L1_TLB_0: l1-tlb { qcom,dump-size = <0x2000>; }; }; CPU1: cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L1_I_1: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9040>; }; L1_D_1: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9040>; }; L1_TLB_1: l1-tlb { qcom,dump-size = <0x2000>; }; }; CPU2: cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L1_I_2: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9040>; }; L1_D_2: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9040>; }; L1_TLB_2: l1-tlb { qcom,dump-size = <0x2000>; }; }; CPU3: cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L1_I_3: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9040>; }; L1_D_3: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9040>; }; L1_TLB_3: l1-tlb { qcom,dump-size = <0x2000>; }; }; CPU4: cpu@100 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1638>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; next-level-cache = <&L2_1>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_1: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; }; L1_I_100: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x12000>; }; L1_D_100: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x12000>; }; L1_TLB_100: l1-tlb { qcom,dump-size = <0x4800>; }; }; CPU5: cpu@101 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; capacity-dmips-mhz = <1638>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; next-level-cache = <&L2_1>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L1_I_101: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x12000>; }; L1_D_101: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x12000>; }; L1_TLB_101: l1-tlb { qcom,dump-size = <0x4800>; }; }; CPU6: cpu@102 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x102>; enable-method = "psci"; capacity-dmips-mhz = <1638>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; next-level-cache = <&L2_1>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L1_I_102: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x12000>; }; L1_D_102: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x12000>; }; L1_TLB_102: l1-tlb { qcom,dump-size = <0x4800>; }; }; CPU7: cpu@103 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x103>; enable-method = "psci"; capacity-dmips-mhz = <1638>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; next-level-cache = <&L2_1>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L1_I_103: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x12000>; }; L1_D_103: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x12000>; }; L1_TLB_103: l1-tlb { qcom,dump-size = <0x4800>; }; }; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; }; cluster1 { core0 { cpu = <&CPU4>; }; core1 { cpu = <&CPU5>; }; core2 { cpu = <&CPU6>; }; core3 { cpu = <&CPU7>; }; }; }; }; energy_costs: energy-costs { compatible = "sched-energy"; CPU_COST_0: core-cost0 { busy-cost-data = < 300000 12 614400 22 864000 39 1017600 54 1305600 83 1420800 102 1612800 130 1804800 172 >; idle-cost-data = < 10 8 6 4 >; }; CPU_COST_1: core-cost1 { busy-cost-data = < 300000 211 652800 417 902400 722 1056000 991 1401600 1577 1536000 1932 1804800 2579 2016000 3391 >; idle-cost-data = < 100 60 40 20 >; }; CLUSTER_COST_0: cluster-cost0 { busy-cost-data = < 300000 5 614400 8 864000 9 1017600 12 1305600 18 1420800 21 1612800 27 1804800 36 >; idle-cost-data = < 4 3 2 1 >; }; CLUSTER_COST_1: cluster-cost1 { busy-cost-data = < 300000 38 652800 46 902400 52 1056000 68 1401600 88 1536000 100 1804800 108 2016000 120 >; idle-cost-data = < 4 3 2 1 >; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; chosen { bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; }; soc: soc { }; firmware: firmware { android { compatible = "android,firmware"; vbmeta { compatible = "android,vbmeta"; parts = "vbmeta,boot,system,vendor,dtbo"; }; fstab { compatible = "android,fstab"; vendor { compatble = "android,vendor"; dev = "/dev/block/platform/soc/4804000.ufshc/by-name/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; fsmgr_flags = "wait,slotselect,avb"; status = "ok"; }; }; }; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; hyp_region: hyp_region@45700000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x45700000 0 0x600000>; }; xbl_aop_mem: xbl_aop_mem@45e00000 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x45e00000 0x0 0x140000>; }; sec_apps_mem: sec_apps_region@45fff000 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x45fff000 0x0 0x1000>; }; smem_region: smem@46000000 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x46000000 0x0 0x200000>; }; removed_region: removed_region@46200000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x46200000 0 0x2d00000>; }; pil_modem_mem: modem_region@4b000000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x4b000000 0 0x7e00000>; }; pil_video_mem: pil_video_region@52e00000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x52e00000 0 0x500000>; }; wlan_msa_mem: wlan_msa_region@53300000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x53300000 0 0x200000>; }; pil_cdsp_mem: cdsp_regions@53500000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x53500000 0 0x1e00000>; }; pil_adsp_mem: pil_adsp_region@55300000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x55300000 0 0x1e00000>; }; pil_ipa_fw_mem: ips_fw_region@57100000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x57100000 0 0x10000>; }; pil_ipa_gsi_mem: ipa_gsi_region@57110000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x57110000 0 0x5000>; }; pil_gpu_mem: gpu_region@57115000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x57115000 0 0x2000>; }; cdsp_sec_mem: cdsp_sec_regions@5f800000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x5f800000 0 0x1e00000>; }; qseecom_mem: qseecom_region@5e400000 { compatible = "shared-dma-pool"; no-map; reg = <0 0x5e400000 0 0x1400000>; }; qseecom_ta_mem: qseecom_ta_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; size = <0 0x1000000>; }; secure_display_memory: secure_display_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; size = <0 0x8c00000>; }; adsp_mem: adsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; size = <0 0x800000>; }; sdsp_mem: sdsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; size = <0 0x400000>; }; dump_mem: mem_dump_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; size = <0 0x400000>; }; cont_splash_memory: cont_splash_region@5c000000 { reg = <0x0 0x5c000000 0x0 0x00f00000>; label = "cont_splash_region"; }; dfps_data_memory: dfps_data_region@5cf00000 { reg = <0x0 0x5cf00000 0x0 0x0100000>; label = "dfps_data_region"; }; disp_rdump_memory: disp_rdump_region@5c000000 { reg = <0x0 0x5c000000 0x0 0x00f00000>; label = "disp_rdump_region"; }; /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; size = <0 0x2000000>; linux,cma-default; }; }; }; &soc { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; interrupt-parent = <&intc>; #redistributor-regions = <1>; redistributor-stride = <0x0 0x20000>; reg = <0xf200000 0x10000>, /* GICD */ <0xf300000 0x100000>; /* GICR * 8 */ interrupts = <1 9 4>; }; jtag_mm0: jtagmm@9040000 { compatible = "qcom,jtagv8-mm"; reg = <0x9040000 0x1000>; reg-names = "etm-base"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU0>; }; jtag_mm1: jtagmm@9140000 { compatible = "qcom,jtagv8-mm"; reg = <0x9140000 0x1000>; reg-names = "etm-base"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU1>; }; jtag_mm2: jtagmm@9240000 { compatible = "qcom,jtagv8-mm"; reg = <0x9240000 0x1000>; reg-names = "etm-base"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU2>; }; jtag_mm3: jtagmm@9340000 { compatible = "qcom,jtagv8-mm"; reg = <0x9340000 0x1000>; reg-names = "etm-base"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU3>; }; jtag_mm4: jtagmm@9440000 { compatible = "qcom,jtagv8-mm"; reg = <0x9440000 0x1000>; reg-names = "etm-base"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU4>; }; jtag_mm5: jtagmm@9540000 { compatible = "qcom,jtagv8-mm"; reg = <0x9540000 0x1000>; reg-names = "etm-base"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU5>; }; jtag_mm6: jtagmm@9640000 { compatible = "qcom,jtagv8-mm"; reg = <0x9640000 0x1000>; reg-names = "etm-base"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU6>; }; jtag_mm7: jtagmm@9740000 { compatible = "qcom,jtagv8-mm"; reg = <0x9740000 0x1000>; reg-names = "etm-base"; clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU7>; }; wakegic: wake-gic { compatible = "qcom,mpm-gic-trinket", "qcom,mpm-gic"; interrupts-extended = <&wakegic GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; reg = <0x45f01b8 0x1000>, <0xf011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ reg-names = "vmpm", "ipc"; qcom,num-mpm-irqs = <96>; interrupt-controller; interrupt-parent = <&intc>; #interrupt-cells = <3>; }; wakegpio: wake-gpio { compatible = "qcom,mpm-gpio-trinket", "qcom,mpm-gpio"; interrupt-controller; interrupt-parent = <&intc>; #interrupt-cells = <2>; }; qcom,memshare { compatible = "qcom,memshare"; qcom,client_1 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x0>; qcom,client-id = <0>; qcom,allocate-boot-time; label = "modem"; }; qcom,client_2 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x0>; qcom,client-id = <2>; label = "modem"; }; mem_client_3_size: qcom,client_3 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x500000>; qcom,client-id = <1>; qcom,allocate-on-request; label = "modem"; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <1 1 0xf08>, <1 2 0xf08>, <1 3 0xf08>, <1 0 0xf08>; clock-frequency = <19200000>; }; timer@f120000 { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "arm,armv7-timer-mem"; reg = <0xf120000 0x1000>; clock-frequency = <19200000>; frame@f121000 { frame-number = <0>; interrupts = <0 8 0x4>, <0 7 0x4>; reg = <0xf121000 0x1000>, <0xf122000 0x1000>; }; frame@f123000 { frame-number = <1>; interrupts = <0 9 0x4>; reg = <0xf123000 0x1000>; status = "disabled"; }; frame@f124000 { frame-number = <2>; interrupts = <0 10 0x4>; reg = <0xf124000 0x1000>; status = "disabled"; }; frame@f125000 { frame-number = <3>; interrupts = <0 11 0x4>; reg = <0xf125000 0x1000>; status = "disabled"; }; frame@f126000 { frame-number = <4>; interrupts = <0 12 0x4>; reg = <0xf126000 0x1000>; status = "disabled"; }; frame@f127000 { frame-number = <5>; interrupts = <0 13 0x4>; reg = <0xf127000 0x1000>; status = "disabled"; }; frame@f128000 { frame-number = <6>; interrupts = <0 14 0x4>; reg = <0xf128000 0x1000>; status = "disabled"; }; }; clocks { sleep_clk: sleep-clk { compatible = "fixed-clock"; clock-frequency = <32000>; clock-output-names = "chip_sleep_clk"; #clock-cells = <1>; }; xo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; clock-output-names = "xo_board"; }; }; clock_rpmcc: qcom,rpmcc { compatible = "qcom,rpmcc-trinket"; #clock-cells = <1>; }; clock_gcc: qcom,gcc@1400000 { compatible = "qcom,gcc-trinket", "syscon"; reg = <0x1400000 0x1f0000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; #clock-cells = <1>; #reset-cells = <1>; }; clock_videocc: qcom,videocc@5b00000 { compatible = "qcom,videocc-trinket", "syscon"; reg = <0x5b00000 0x10000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; #clock-cells = <1>; }; clock_dispcc: qcom,dispcc@5f00000 { compatible = "qcom,dispcc-trinket", "syscon"; reg = <0x5f00000 0x20000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; clock-names = "cfg_ahb_clk"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; #clock-cells = <1>; }; clock_gpucc: qcom,gpupcc@5990000 { compatible = "qcom,gpucc-trinket", "syscon"; reg = <0x5990000 0x9000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>; qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>; #clock-cells = <1>; }; mccc_debug: syscon@447d200 { compatible = "syscon"; reg = <0x0447d200 0x100>; }; cpucc_debug: syscon@f11101c { compatible = "syscon"; reg = <0xf11101c 0x4>; }; clock_cpucc: qcom,cpucc@f521000 { compatible = "qcom,clk-cpu-osm-trinket"; reg = <0xf521000 0x1400>, <0xf523000 0x1400>; reg-names = "osm_pwrcl_base", "osm_perfcl_base"; #clock-cells = <1>; }; clock_debugcc: qcom,cc-debug { compatible = "qcom,debugcc-trinket"; qcom,gcc = <&clock_gcc>; qcom,videocc = <&clock_videocc>; qcom,dispcc = <&clock_dispcc>; qcom,gpucc = <&clock_gpucc>; qcom,mccc = <&mccc_debug>; qcom,cpucc = <&cpucc_debug>; clock-names = "cxo"; clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>; #clock-cells = <1>; }; arm64-cpu-erp { compatible = "arm,arm64-cpu-erp"; interrupts = <0 43 4>, <0 44 4>, <0 41 4>, <0 42 4>; interrupt-names = "pri-dbe-irq", "sec-dbe-irq", "pri-ext-irq", "sec-ext-irq"; poll-delay-ms = <5000>; }; ufs_ice: ufsice@4810000 { compatible = "qcom,ice"; reg = <0x4810000 0x8000>; qcom,enable-ice-clk; clock-names = "ufs_core_clk", "bus_clk", "iface_clk", "ice_core_clk"; clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, <&clock_gcc GCC_UFS_PHY_AHB_CLK>, <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; vdd-hba-supply = <&ufs_phy_gdsc>; qcom,msm-bus,name = "ufs_ice_noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 650 0 0>, /* No vote */ <1 650 1000 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "MAX"; qcom,instance-type = "ufs"; }; ufsphy_mem: ufsphy_mem@4807000 { reg = <0x4807000 0xdb8>; /* PHY regs */ reg-names = "phy_mem"; #phy-cells = <0>; lanes-per-direction = <1>; clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK1>, <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; status = "disabled"; }; ufshc_mem: ufshc@4804000 { compatible = "qcom,ufshc"; reg = <0x4804000 0x3000>, <0x4810000 0x8000>; reg-names = "ufs_mem", "ufs_ice"; interrupts = <0 356 0>; phys = <&ufsphy_mem>; phy-names = "ufsphy"; lanes-per-direction = <1>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ spm-level = <5>; clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk"; clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, <&clock_gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, <&clock_gcc GCC_UFS_PHY_AHB_CLK>, <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&clock_rpmcc RPM_SMD_LN_BB_CLK1>, <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; freq-table-hz = <50000000 240000000>, <0 0>, <0 0>, <37500000 150000000>, <75000000 300000000>, <0 0>, <0 0>, <0 0>; qcom,msm-bus,name = "ufshc_mem"; qcom,msm-bus,num-cases = <12>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = /* * During HS G3 UFS runs at nominal voltage corner, vote * higher bandwidth to push other buses in the data path * to run at nominal to achieve max throughput. * 4GBps pushes BIMC to run at nominal. * 200MBps pushes CNOC to run at nominal. * Vote for half of this bandwidth for HS G3 1-lane. * For max bandwidth, vote high enough to push the buses * to run in turbo voltage corner. */ <123 512 0 0>, <1 757 0 0>, /* No vote */ <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "MAX"; /* PM QoS */ qcom,pm-qos-cpu-groups = <0x0f 0xf0>; qcom,pm-qos-cpu-group-latency-us = <26 26>; qcom,pm-qos-default-cpu = <0>; pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; pinctrl-0 = <&ufs_dev_reset_assert>; pinctrl-1 = <&ufs_dev_reset_deassert>; resets = <&clock_gcc GCC_UFS_PHY_BCR>; reset-names = "core_reset"; non-removable; status = "disabled"; }; qcom,msm-imem@c125000 { compatible = "qcom,msm-imem"; reg = <0xc125000 0x1000>; ranges = <0x0 0xc125000 0x1000>; #address-cells = <1>; #size-cells = <1>; mem_dump_table@10 { compatible = "qcom,msm-imem-mem_dump_table"; reg = <0x10 8>; }; restart_reason@65c { compatible = "qcom,msm-imem-restart_reason"; reg = <0x65c 4>; }; dload_type@1c { compatible = "qcom,msm-imem-dload-type"; reg = <0x1c 0x4>; }; boot_stats@6b0 { compatible = "qcom,msm-imem-boot_stats"; reg = <0x6b0 32>; }; kaslr_offset@6d0 { compatible = "qcom,msm-imem-kaslr_offset"; reg = <0x6d0 12>; }; pil@94c { compatible = "qcom,msm-imem-pil"; reg = <0x94c 200>; }; diag_dload@c8 { compatible = "qcom,msm-imem-diag-dload"; reg = <0xc8 200>; }; }; restart@440b000 { compatible = "qcom,pshold"; reg = <0x440b000 0x4>, <0x03d3000 0x4>; reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; qcom,mpm2-sleep-counter@4403000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0x4403000 0x1000>; clock-frequency = <32768>; }; qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; }; thermal_zones: thermal-zones {}; dcc: dcc_v2@1be2000 { compatible = "qcom,dcc-v2"; reg = <0x1be2000 0x1000>, <0x1bef000 0x1000>; reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x1000>; }; tsens0: tsens@4410000 { compatible = "qcom,sm6150-tsens"; reg = <0x4410000 0x8>, <0x4411000 0x1ff>; reg-names = "tsens_srot_physical", "tsens_tm_physical"; interrupts = <0 275 0>, <0 190 0>; interrupt-names = "tsens-upper-lower", "tsens-critical"; #thermal-sensor-cells = <1>; }; cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; qcom,irq-is-percpu; interrupts = <1 6 4>; }; eud: qcom,msm-eud@1610000 { compatible = "qcom,msm-eud"; interrupt-names = "eud_irq"; interrupts = ; reg = <0x1610000 0x2000>, <0x1612000 0x1000>; reg-names = "eud_base", "eud_mode_mgr2"; qcom,secure-eud-en; qcom,eud-clock-vote-req; clocks = <&clock_gcc GCC_AHB2PHY_USB_CLK>; clock-names = "eud_ahb2phy_clk"; status = "ok"; }; qcom,msm-gladiator-v2@f100000 { compatible = "qcom,msm-gladiator-v2"; reg = <0xf100000 0xdc00>; reg-names = "gladiator_base"; interrupts = <0 22 0>; clock-names = "atb_clk"; clocks = <&clock_rpmcc RPM_QDSS_CLK>; }; pil_modem: qcom,mss@6080000 { compatible = "qcom,pil-tz-generic"; reg = <0x6080000 0x100>; clocks = <&clock_rpmcc CXO_SMD_PIL_MSS_CLK>; clock-names = "xo"; qcom,proxy-clock-names = "xo"; vdd_cx-supply = <&VDD_CX_LEVEL>; qcom,vdd_cx-uV-uA = ; qcom,mas-crypto = <&mas_crypto_c0>; qcom,proxy-reg-names = "vdd_cx"; qcom,firmware-name = "modem"; memory-region = <&pil_modem_mem>; qcom,proxy-timeout-ms = <10000>; qcom,sysmon-id = <0>; qcom,ssctl-instance-id = <0x12>; qcom,pas-id = <4>; qcom,smem-id = <421>; qcom,minidump-id = <3>; qcom,aux-minidump-ids = <4>; qcom,complete-ramdump; /* Inputs from mss */ interrupts-extended = <&wakegic 0 307 1>, <&modem_smp2p_in 0 0>, <&modem_smp2p_in 2 0>, <&modem_smp2p_in 1 0>, <&modem_smp2p_in 3 0>, <&modem_smp2p_in 7 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", "qcom,stop-ack", "qcom,shutdown-ack"; /* Outputs to mss */ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "qcom,force-stop"; }; rpm_bus: qcom,rpm-smd { compatible = "qcom,rpm-smd"; rpm-channel-name = "rpm_requests"; interrupts = ; rpm-channel-type = <15>; /* SMD_APPS_RPM */ }; wdog: qcom,wdt@f017000 { compatible = "qcom,msm-watchdog"; reg = <0xf017000 0x1000>; reg-names = "wdt-base"; interrupts = <0 3 0>, <0 4 0>; qcom,bark-time = <11000>; qcom,pet-time = <9360>; qcom,ipi-ping; qcom,wakeup-enable; qcom,scandump-sizes = <0x40000>; }; qcom,chd_silver { compatible = "qcom,core-hang-detect"; label = "silver"; qcom,threshold-arr = <0xf1880b0 0xf1980b0 0xf1a80b0 0xf1b80b0>; qcom,config-arr = <0xf1880b8 0xf1980b8 0xf1a80b8 0xf1b80b8>; }; qcom,chd_gold { compatible = "qcom,core-hang-detect"; label = "gold"; qcom,threshold-arr = <0xf0880b0 0xf0980b0 0xf0a80b0 0xf0b80b0>; qcom,config-arr = <0xf0880b8 0xf0980b8 0xf0a80b8 0xf0b80b8>; }; qcom,ghd { compatible = "qcom,gladiator-hang-detect"; qcom,threshold-arr = <0x0f1d141c 0x0f1d1420 0x0f1d1424 0x0f1d1428 0x0f1d142c 0x0f1d1430>; qcom,config-reg = <0x0f1d1434>; }; qcom,sps { compatible = "qcom,msm-sps-4k"; qcom,pipe-attr-ee; }; gpi_dma0: qcom,gpi-dma@0x04a00000 { #dma-cells = <5>; compatible = "qcom,gpi-dma"; reg = <0x04a00000 0x60000>; reg-names = "gpi-top"; interrupts = <0 335 0>, <0 336 0>, <0 337 0>, <0 338 0>, <0 339 0>, <0 340 0>, <0 341 0>, <0 342 0>; qcom,ev-factor = <2>; qcom,max-num-gpii = <8>; qcom,gpii-mask = <0x1f>; iommus = <&apps_smmu 0x0136 0x0>; qcom,smmu-cfg = <0x1>; qcom,iova-range = <0x0 0x100000 0x0 0x100000>; status = "ok"; }; gpi_dma1: qcom,gpi-dma@0x04c00000 { #dma-cells = <5>; compatible = "qcom,gpi-dma"; reg = <0x04c00000 0x60000>; reg-names = "gpi-top"; interrupts = <0 314 0>, <0 315 0>, <0 316 0>, <0 317 0>, <0 318 0>, <0 319 0>, <0 320 0>, <0 321 0>; qcom,ev-factor = <2>; qcom,max-num-gpii = <8>; qcom,gpii-mask = <0x0f>; qcom,smmu-cfg = <0x1>; qcom,iova-range = <0x0 0x100000 0x0 0x100000>; iommus = <&apps_smmu 0x0156 0x0>; status = "ok"; }; qcom,lpass@ab00000 { compatible = "qcom,pil-tz-generic"; reg = <0xab00000 0x00100>; vdd_cx-supply = <&VDD_CX_LEVEL>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = ; qcom,mas-crypto = <&mas_crypto_c0>; clocks = <&clock_rpmcc CXO_SMD_PIL_LPASS_CLK>; clock-names = "xo"; qcom,proxy-clock-names = "xo"; qcom,pas-id = <1>; qcom,proxy-timeout-ms = <10000>; qcom,smem-id = <423>; qcom,sysmon-id = <1>; qcom,ssctl-instance-id = <0x14>; qcom,firmware-name = "adsp"; memory-region = <&pil_adsp_mem>; qcom,complete-ramdump; /* Inputs from lpass */ interrupts-extended = <&wakegic 0 396 1>, <&adsp_smp2p_in 0 0>, <&adsp_smp2p_in 2 0>, <&adsp_smp2p_in 1 0>, <&adsp_smp2p_in 3 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", "qcom,stop-ack"; /* Outputs to lpass */ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "qcom,force-stop"; }; qcom,turing@b300000 { compatible = "qcom,pil-tz-generic"; reg = <0xb300000 0x100000>; vdd_cx-supply = <&VDD_CX_LEVEL>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = ; qcom,mas-crypto = <&mas_crypto_c0>; clocks = <&clock_rpmcc CXO_SMD_PIL_CDSP_CLK>; clock-names = "xo"; qcom,proxy-clock-names = "xo"; qcom,pas-id = <18>; qcom,proxy-timeout-ms = <10000>; qcom,smem-id = <601>; qcom,sysmon-id = <7>; qcom,ssctl-instance-id = <0x17>; qcom,firmware-name = "cdsp"; memory-region = <&pil_cdsp_mem>; qcom,complete-ramdump; /* Inputs from turing */ interrupts-extended = <&wakegic 0 265 1>, <&cdsp_smp2p_in 0 0>, <&cdsp_smp2p_in 2 0>, <&cdsp_smp2p_in 1 0>, <&cdsp_smp2p_in 3 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", "qcom,stop-ack"; /* Outputs to turing */ qcom,smem-states = <&cdsp_smp2p_out 0>; qcom,smem-state-names = "qcom,force-stop"; }; cpuss_dump: cpuss_dump { compatible = "qcom,cpuss-dump"; qcom,l1_i_cache0 { qcom,dump-node = <&L1_I_0>; qcom,dump-id = <0x60>; }; qcom,l1_i_cache1 { qcom,dump-node = <&L1_I_1>; qcom,dump-id = <0x61>; }; qcom,l1_i_cache2 { qcom,dump-node = <&L1_I_2>; qcom,dump-id = <0x62>; }; qcom,l1_i_cache3 { qcom,dump-node = <&L1_I_3>; qcom,dump-id = <0x63>; }; qcom,l1_i_cache100 { qcom,dump-node = <&L1_I_100>; qcom,dump-id = <0x64>; }; qcom,l1_i_cache101 { qcom,dump-node = <&L1_I_101>; qcom,dump-id = <0x65>; }; qcom,l1_i_cache102 { qcom,dump-node = <&L1_I_102>; qcom,dump-id = <0x66>; }; qcom,l1_i_cache103 { qcom,dump-node = <&L1_I_103>; qcom,dump-id = <0x67>; }; qcom,l1_d_cache0 { qcom,dump-node = <&L1_D_0>; qcom,dump-id = <0x80>; }; qcom,l1_d_cache1 { qcom,dump-node = <&L1_D_1>; qcom,dump-id = <0x81>; }; qcom,l1_d_cache2 { qcom,dump-node = <&L1_D_2>; qcom,dump-id = <0x82>; }; qcom,l1_d_cache3 { qcom,dump-node = <&L1_D_3>; qcom,dump-id = <0x83>; }; qcom,l1_d_cache100 { qcom,dump-node = <&L1_D_100>; qcom,dump-id = <0x84>; }; qcom,l1_d_cache101 { qcom,dump-node = <&L1_D_101>; qcom,dump-id = <0x85>; }; qcom,l1_d_cache102 { qcom,dump-node = <&L1_D_102>; qcom,dump-id = <0x86>; }; qcom,l1_d_cache103 { qcom,dump-node = <&L1_D_103>; qcom,dump-id = <0x87>; }; qcom,l1_tlb_dump0 { qcom,dump-node = <&L1_TLB_0>; qcom,dump-id = <0x120>; }; qcom,l1_tlb_dump1 { qcom,dump-node = <&L1_TLB_1>; qcom,dump-id = <0x121>; }; qcom,l1_tlb_dump2 { qcom,dump-node = <&L1_TLB_2>; qcom,dump-id = <0x122>; }; qcom,l1_tlb_dump3 { qcom,dump-node = <&L1_TLB_3>; qcom,dump-id = <0x123>; }; qcom,l1_tlb_dump100 { qcom,dump-node = <&L1_TLB_100>; qcom,dump-id = <0x124>; }; qcom,l1_tlb_dump101 { qcom,dump-node = <&L1_TLB_101>; qcom,dump-id = <0x125>; }; qcom,l1_tlb_dump102 { qcom,dump-node = <&L1_TLB_102>; qcom,dump-id = <0x126>; }; qcom,l1_tlb_dump103 { qcom,dump-node = <&L1_TLB_103>; qcom,dump-id = <0x127>; }; }; mem_dump { compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; rpm_sw { qcom,dump-size = <0x28000>; qcom,dump-id = <0xea>; }; pmic { qcom,dump-size = <0x10000>; qcom,dump-id = <0xe4>; }; fcm { qcom,dump-size = <0x8400>; qcom,dump-id = <0xee>; }; tmc_etf { qcom,dump-size = <0x8000>; qcom,dump-id = <0xf0>; }; etr_reg { qcom,dump-size = <0x1000>; qcom,dump-id = <0x100>; }; etf_reg { qcom,dump-size = <0x1000>; qcom,dump-id = <0x101>; }; misc_data { qcom,dump-size = <0x1000>; qcom,dump-id = <0xe8>; }; }; tcsr_mutex_block: syscon@00340000 { compatible = "syscon"; reg = <0x00340000 0x20000>; }; tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_block 0 0x1000>; #hwlock-cells = <1>; }; smem: qcom,smem { compatible = "qcom,smem"; memory-region = <&smem_region>; hwlocks = <&tcsr_mutex 3>; }; rpm_msg_ram: memory@045F0000 { compatible = "qcom,rpm-msg-ram"; reg = <0x045f0000 0x7000>; }; apcs_glb: mailbox@0F111000 { compatible = "qcom,trinket-apcs-hmss-global"; reg = <0x0F111000 0x1000>; #mbox-cells = <1>; }; qcom,msm-cdsp-loader { compatible = "qcom,cdsp-loader"; qcom,proc-img-to-load = "cdsp"; }; qcom,msm-adsprpc-mem { compatible = "qcom,msm-adsprpc-mem-region"; memory-region = <&adsp_mem>; restrict-access; }; qcom,msm_fastrpc { compatible = "qcom,msm-fastrpc-compute"; qcom,rpc-latency-us = <611>; qcom,adsp-remoteheap-vmid = <22 37>; qcom,fastrpc-adsp-audio-pdr; qcom,fastrpc-adsp-sensors-pdr; qcom,msm_fastrpc_compute_cb1 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x0C01 0x0>; }; qcom,msm_fastrpc_compute_cb2 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x0C02 0x0>; }; qcom,msm_fastrpc_compute_cb3 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x0C03 0x0>; }; qcom,msm_fastrpc_compute_cb4 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x0C04 0x0>; }; qcom,msm_fastrpc_compute_cb5 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x0C05 0x0>; }; qcom,msm_fastrpc_compute_cb6 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x0C06 0x0>; }; qcom,msm_fastrpc_compute_cb9 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; qcom,secure-context-bank; iommus = <&apps_smmu 0x0C09 0x0>; }; qcom,msm_fastrpc_compute_cb10 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "adsprpc-smd"; iommus = <&apps_smmu 0x0043 0x0>, <&apps_smmu 0x0044 0x0>; shared-sid = <2>; shared-cb = <5>; }; }; rpm-glink { compatible = "qcom,glink-rpm"; interrupts = ; qcom,rpm-msg-ram = <&rpm_msg_ram>; mboxes = <&apcs_glb 0>; qcom,rpm_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_adsp>, <&glink_cdsp>; }; }; qcom,glink { compatible = "qcom,glink"; #address-cells = <1>; #size-cells = <1>; ranges; glink_modem: modem { qcom,remote-pid = <1>; transport = "smem"; mboxes = <&apcs_glb 12>; mbox-names = "mpss_smem"; interrupts = ; label = "modem"; qcom,glink-label = "mpss"; qcom,modem_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,msm_fastrpc_rpmsg { compatible = "qcom,msm-fastrpc-rpmsg"; qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x64 64>; }; qcom,modem_ds { qcom,glink-channels = "DS"; qcom,intents = <0x4000 2>; }; qcom,modem_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_adsp>, <&glink_cdsp>; }; }; glink_adsp: adsp { qcom,remote-pid = <2>; transport = "smem"; mboxes = <&apcs_glb 8>; mbox-names = "adsp_smem"; interrupts = ; label = "adsp"; qcom,glink-label = "lpass"; qcom,adsp_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,apr_tal_rpmsg { qcom,glink-channels = "apr_audio_svc"; qcom,intents = <0x200 20>; }; qcom,msm_fastrpc_rpmsg { compatible = "qcom,msm-fastrpc-rpmsg"; qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x64 64>; }; qcom,adsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_cdsp>; }; }; glink_cdsp: cdsp { qcom,remote-pid = <5>; transport = "smem"; mboxes = <&apcs_glb 28>; mbox-names = "cdsp_smem"; interrupts = ; label = "cdsp"; qcom,glink-label = "cdsp"; qcom,cdsp_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,msm_fastrpc_rpmsg { compatible = "qcom,msm-fastrpc-rpmsg"; qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x64 64>; }; qcom,msm_cdsprm_rpmsg { compatible = "qcom,msm-cdsprm-rpmsg"; qcom,glink-channels = "cdsprmglink-apps-dsp"; qcom,intents = <0x20 12>; msm_cdsp_rm: qcom,msm_cdsp_rm { compatible = "qcom,msm-cdsp-rm"; qcom,qos-latency-us = <44>; qcom,qos-maxhold-ms = <20>; #cooling-cells = <2>; }; msm_hvx_rm: qcom,msm_hvx_rm { compatible = "qcom,msm-hvx-rm"; #cooling-cells = <2>; }; }; qcom,cdsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_adsp>; }; }; glink_spi_xprt_wdsp: wdsp { qcom,remote-pid = <10>; transport = "spi"; tx-descriptors = <0x12000 0x12004>; rx-descriptors = <0x1200c 0x12010>; qcom,wdsp_ctrl { qcom,glink-channels = "g_glink_ctrl"; qcom,intents = <0x400 1>; }; qcom,wdsp_ild { qcom,glink-channels = "g_glink_persistent_data_ild"; }; qcom,wdsp_nild { qcom,glink-channels = "g_glink_persistent_data_nild"; }; qcom,wdsp_data { qcom,glink-channels = "g_glink_audio_data"; qcom,intents = <0x1000 2>; }; qcom,diag_data { qcom,glink-channels = "DIAG_DATA"; qcom,intents = <0x4000 2>; }; qcom,diag_ctrl { qcom,glink-channels = "DIAG_CTRL"; qcom,intents = <0x4000 1>; }; qcom,diag_cmd { qcom,glink-channels = "DIAG_CMD"; qcom,intents = <0x4000 1 >; }; }; }; qcom,glinkpkt { compatible = "qcom,glinkpkt"; qcom,glinkpkt-at-mdm0 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DS"; qcom,glinkpkt-dev-name = "at_mdm0"; }; qcom,glinkpkt-apr-apps2 { qcom,glinkpkt-edge = "adsp"; qcom,glinkpkt-ch-name = "apr_apps2"; qcom,glinkpkt-dev-name = "apr_apps2"; }; qcom,glinkpkt-data40-cntl { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA40_CNTL"; qcom,glinkpkt-dev-name = "smdcntl8"; }; qcom,glinkpkt-data1 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA1"; qcom,glinkpkt-dev-name = "smd7"; }; qcom,glinkpkt-data4 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA4"; qcom,glinkpkt-dev-name = "smd8"; }; qcom,glinkpkt-data11 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA11"; qcom,glinkpkt-dev-name = "smd11"; }; }; qcom,smp2p_sleepstate { compatible = "qcom,smp2p-sleepstate"; qcom,smem-states = <&sleepstate_smp2p_out 0>; interrupt-parent = <&sleepstate_smp2p_in>; interrupts = <0 0>; interrupt-names = "smp2p-sleepstate-in"; }; qcom,smp2p-modem { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupts = ; mboxes = <&apcs_glb 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; modem_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; modem_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; /* ipa - inbound entry from mss */ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { qcom,entry-name = "wlan"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupts = ; mboxes = <&apcs_glb 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { qcom,entry-name = "rdbg"; #qcom,smem-state-cells = <1>; }; smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { qcom,entry-name = "rdbg"; interrupt-controller; #interrupt-cells = <2>; }; sleepstate_smp2p_out: sleepstate-out { qcom,entry-name = "sleepstate"; #qcom,smem-state-cells = <1>; }; sleepstate_smp2p_in: qcom,sleepstate-in { qcom,entry-name = "sleepstate_see"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupts = ; mboxes = <&apcs_glb 30>; qcom,local-pid = <0>; qcom,remote-pid = <5>; cdsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; cdsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { qcom,entry-name = "rdbg"; #qcom,smem-state-cells = <1>; }; smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { qcom,entry-name = "rdbg"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom_seecom: qseecom@46d00000 { compatible = "qcom,qseecom"; reg = <0x46d00000 0x2200000>; reg-names = "secapp-region"; memory-region = <&qseecom_mem>; qcom,hlos-num-ce-hw-instances = <1>; qcom,hlos-ce-hw-instance = <0>; qcom,qsee-ce-hw-instance = <0>; qcom,disk-encrypt-pipe-pair = <2>; qcom,support-fde; qcom,fde-key-size; qcom,appsbl-qseecom-support; qcom,commonlib64-loaded-by-uefi; qcom,msm-bus,name = "qseecom-noc"; qcom,msm-bus,num-cases = <4>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <55 512 0 0>, <55 512 200000 400000>, <55 512 300000 800000>, <55 512 400000 1000000>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; clocks = <&clock_rpmcc QSEECOM_CE1_CLK>, <&clock_rpmcc QSEECOM_CE1_CLK>, <&clock_rpmcc QSEECOM_CE1_CLK>, <&clock_rpmcc QSEECOM_CE1_CLK>; qcom,ce-opp-freq = <171430000>; qcom,qsee-reentrancy-support = <2>; }; qcom_smcinvoke: smcinvoke@46d00000 { compatible = "qcom,smcinvoke"; reg = <0x46d00000 0x2200000>; reg-names = "secapp-region"; }; qcom_rng: qrng@1b53000 { compatible = "qcom,msm-rng"; reg = <0x1b53000 0x1000>; qcom,msm-rng-iface-clk; qcom,no-qrng-config; qcom,msm-bus,name = "msm-rng-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 618 0 0>, /* No vote */ <1 618 0 300000>; /* 75 MHz */ clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; clock-names = "iface_clk"; }; qcom_tzlog: tz-log@0c125720 { compatible = "qcom,tz-log"; reg = <0x0c125720 0x3000>; qcom,hyplog-enabled; hyplog-address-offset = <0x410>; hyplog-size-offset = <0x414>; }; spmi_bus: qcom,spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x1c40000 0x1100>, <0x1e00000 0x2000000>, <0x3e00000 0x100000>, <0x3f00000 0xa0000>, <0x1c0a000 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <1>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <4>; cell-index = <0>; }; qcom,rmtfs_sharedmem@0 { compatible = "qcom,sharedmem-uio"; reg = <0x0 0x200000>; reg-names = "rmtfs"; qcom,client-id = <0x00000001>; qcom,guard-memory; qcom,vm-nav-path; }; qcom_cedev: qcedev@1b20000 { compatible = "qcom,qcedev"; reg = <0x1b20000 0x20000>, <0x1b04000 0x24000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <0 247 0>; qcom,bam-pipe-pair = <3>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,ce-hw-shared; qcom,bam-ee = <0>; qcom,msm-bus,name = "qcedev-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <55 512 0 0>, <55 512 393600 393600>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; clocks = <&clock_rpmcc QCEDEV_CE1_CLK>, <&clock_rpmcc QCEDEV_CE1_CLK>, <&clock_rpmcc QCEDEV_CE1_CLK>, <&clock_rpmcc QCEDEV_CE1_CLK>; qcom,ce-opp-freq = <171430000>; qcom,smmu-s1-enable; iommus = <&apps_smmu 0x01A6 0x0011>, <&apps_smmu 0x01B6 0x0011>; }; qcom_msmhdcp: qcom,msm_hdcp { compatible = "qcom,msm-hdcp"; }; qcom_crypto: qcrypto@1b20000 { compatible = "qcom,qcrypto"; reg = <0x1b20000 0x20000>, <0x1b04000 0x24000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <0 247 0>; qcom,bam-pipe-pair = <2>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,bam-ee = <0>; qcom,ce-hw-shared; qcom,clk-mgmt-sus-res; qcom,msm-bus,name = "qcrypto-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <55 512 0 0>, <55 512 393600 393600>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; clocks = <&clock_rpmcc QCRYPTO_CE1_CLK>, <&clock_rpmcc QCRYPTO_CE1_CLK>, <&clock_rpmcc QCRYPTO_CE1_CLK>, <&clock_rpmcc QCRYPTO_CE1_CLK>; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; qcom,use-sw-ahash-algo; qcom,use-sw-aead-algo; qcom,use-sw-hmac-algo; qcom,smmu-s1-enable; iommus = <&apps_smmu 0x01A4 0x0011>, <&apps_smmu 0x01B4 0x0011>; }; bluetooth: bt_wcn3990 { compatible = "qca,wcn3990"; qca,bt-vdd-io-supply = <&pm6125_l9>; qca,bt-vdd-core-supply = <&pm6125_l17>; qca,bt-vdd-pa-supply = <&pm6125_l23>; qca,bt-vdd-xtal-supply = <&pm6125_l16>; qca,bt-vdd-io-voltage-level = <1700000 1900000>; /* IO */ qca,bt-vdd-core-voltage-level = <1304000 1304000>; /* RFA */ qca,bt-vdd-pa-voltage-level = <3000000 3400000>; /*chain0 */ qca,bt-vdd-xtal-voltage-level = <1700000 1900000>; /* XO */ qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ }; slim_aud: slim@a2c0000 { cell-index = <1>; compatible = "qcom,slim-ngd"; reg = <0xa2c0000 0x2c000>, <0xa284000 0x2a000>; reg-names = "slimbus_physical", "slimbus_bam_physical"; interrupts = <0 397 0>, <0 398 0>; interrupt-names = "slimbus_irq", "slimbus_bam_irq"; qcom,apps-ch-pipes = <0x7c0000>; qcom,ea-pc = <0x310>; status = "disabled"; qcom,iommu-s1-bypass; iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb { compatible = "qcom,iommu-slim-ctrl-cb"; iommus = <&apps_smmu 0x66 0x0>, <&apps_smmu 0x6d 0x0>, <&apps_smmu 0x6e 0x1>, <&apps_smmu 0x70 0x1>; }; }; slim_qca: slim@a340000 { cell-index = <3>; compatible = "qcom,slim-ngd"; reg = <0xa340000 0x2c000>, <0xa304000 0x20000>; reg-names = "slimbus_physical", "slimbus_bam_physical"; interrupts = <0 403 0>, <0 404 0>; interrupt-names = "slimbus_irq", "slimbus_bam_irq"; status = "ok"; qcom,iommu-s1-bypass; iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb { compatible = "qcom,iommu-slim-ctrl-cb"; iommus = <&apps_smmu 0x73 0x0>; }; /* Slimbus Slave DT for WCN3990 */ btfmslim_codec: wcn3990 { compatible = "qcom,btfmslim_slave"; elemental-addr = [00 01 20 02 17 02]; qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; }; }; sdcc1_ice: sdcc1ice@4748000{ compatible = "qcom,ice"; reg = <0x4748000 0x8000>; qcom,enable-ice-clk; clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk"; clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>, <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>, <&clock_gcc GCC_SDCC1_AHB_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>; qcom,op-freq-hz = <300000000>, <0>, <0>, <0>; qcom,msm-bus,name = "sdcc_ice_noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 757 0 0>, /* No vote */ <1 757 1000 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "MAX"; qcom,instance-type = "sdcc"; }; sdhc_1: sdhci@4744000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x4744000 0x1000>, <0x4745000 0x1000>, <0x4748000 0x8000>; reg-names = "hc_mem", "cmdq_mem", "cmdq_ice"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <8>; qcom,large-address-bus; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>; qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; qcom,devfreq,freq-table = <50000000 200000000>; qcom,msm-bus,name = "sdhc1"; qcom,msm-bus,num-cases = <9>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = /* No vote */ <78 512 0 0>, <1 606 0 0>, /* 400 KB/s*/ <78 512 1046 1600>, <1 606 1600 1600>, /* 20 MB/s */ <78 512 20480 80000>, <1 606 80000 80000>, /* 25 MB/s */ <78 512 25600 100000>, <1 606 50000 100000>, /* 50 MB/s */ <78 512 51200 200000>, <1 606 65000 100000>, /* 100 MB/s */ <78 512 102400 200000>, <1 606 65000 100000>, /* 200 MB/s */ <78 512 204800 400000>, <1 606 300000 300000>, /* 400 MB/s */ <78 512 204800 400000>, <1 606 300000 300000>, /* Max. bandwidth */ <78 512 1338562 4096000>, <1 606 1338562 4096000>; qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100750000 200000000 400000000 4294967295>; /* PM QoS */ qcom,pm-qos-irq-type = "affine_irq"; qcom,pm-qos-irq-latency = <40 40>; qcom,pm-qos-cpu-groups = <0x0f 0xf0>; qcom,pm-qos-cmdq-latency-us = <40 40>, <40 40>; qcom,pm-qos-legacy-latency-us = <40 40>, <40 40>; qcom,scaling-lower-bus-speed-mode = "DDR52"; clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>, <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface_clk", "core_clk", "ice_core_clk"; qcom,ice-clk-rates = <300000000 75000000>; /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040873>; qcom,nonremovable; status = "disabled"; }; sdhc_2: sdhci@4784000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x4784000 0x1000>; reg-names = "hc_mem"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <4>; qcom,large-address-bus; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 202000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; qcom,devfreq,freq-table = <50000000 202000000>; qcom,msm-bus,name = "sdhc2"; qcom,msm-bus,num-cases = <8>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = /* No vote */ <81 512 0 0>, <1 608 0 0>, /* 400 KB/s*/ <81 512 1046 3200>, <1 608 1600 1600>, /* 20 MB/s */ <81 512 52286 160000>, <1 608 80000 80000>, /* 25 MB/s */ <81 512 65360 200000>, <1 608 100000 100000>, /* 50 MB/s */ <81 512 130718 400000>, <1 608 133320 133320>, /* 100 MB/s */ <81 512 261438 400000>, <1 608 150000 150000>, /* 200 MB/s */ <81 512 261438 800000>, <1 608 300000 300000>, /* Max. bandwidth */ <81 512 1338562 4096000>, <1 608 1338562 4096000>; qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100750000 200000000 4294967295>; /* PM QoS */ qcom,pm-qos-irq-type = "affine_irq"; qcom,pm-qos-irq-latency = <40 40>; qcom,pm-qos-cpu-groups = <0x0f 0xf0>; qcom,pm-qos-legacy-latency-us = <40 40>, <40 40>; clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, <&clock_gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface_clk", "core_clk"; /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040873>; status = "disabled"; }; qcom,msm_gsi { compatible = "qcom,msm_gsi"; }; qcom,rmnet-ipa { compatible = "qcom,rmnet-ipa3"; qcom,rmnet-ipa-ssr; qcom,ipa-platform-type-msm; qcom,ipa-advertise-sg-support; qcom,ipa-napi-enable; }; ipa_hw: qcom,ipa@5800000 { compatible = "qcom,ipa"; reg = <0x5800000 0x34000>, <0x5804000 0x2c000>; reg-names = "ipa-base", "gsi-base"; interrupts = <0 257 0>, <0 259 0>; interrupt-names = "ipa-irq", "gsi-irq"; qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */ qcom,ipa-hw-mode = <0>; qcom,ee = <0>; qcom,use-ipa-tethering-bridge; qcom,modem-cfg-emb-pipe-flt; qcom,ipa-wdi2; qcom,ipa-wdi2_over_gsi; qcom,ipa-endp-delay-wa; qcom,ipa-fltrt-not-hashable; qcom,use-64-bit-dma-mask; qcom,arm-smmu; qcom,smmu-fast-map; qcom,use-ipa-pm; clocks = <&clock_rpmcc RPM_SMD_IPA_CLK>; clock-names = "core_clk"; qcom,msm-bus,name = "ipa"; qcom,msm-bus,num-cases = <5>; qcom,msm-bus,num-paths = <3>; qcom,msm-bus,vectors-KBps = /* No vote */ , , , /* SVS2 */ , , , /* SVS */ , , , /* NOMINAL */ , , , /* TURBO */ , , ; qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; qcom,throughput-threshold = <310 600 1000>; qcom,scaling-exceptions = <>; /* smp2p information */ qcom,smp2p_map_ipa_1_out { compatible = "qcom,smp2p-map-ipa-1-out"; qcom,smem-states = <&smp2p_ipa_1_out 0>; qcom,smem-state-names = "ipa-smp2p-out"; }; qcom,smp2p_map_ipa_1_in { compatible = "qcom,smp2p-map-ipa-1-in"; interrupts-extended = <&smp2p_ipa_1_in 0 0>; interrupt-names = "ipa-smp2p-in"; }; }; ipa_smmu_ap: ipa_smmu_ap { compatible = "qcom,ipa-smmu-ap-cb"; iommus = <&apps_smmu 0x00E0 0x0>; qcom,iova-mapping = <0x10000000 0x30000000>; /* modem tables in IMEM */ qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>; }; ipa_smmu_wlan: ipa_smmu_wlan { compatible = "qcom,ipa-smmu-wlan-cb"; iommus = <&apps_smmu 0x00E1 0x0>; /* ipa-uc ram */ qcom,additional-mapping = <0x5860000 0x5860000 0x80000>; }; ipa_smmu_uc: ipa_smmu_uc { compatible = "qcom,ipa-smmu-uc-cb"; iommus = <&apps_smmu 0x00E2 0x0>; qcom,iova-mapping = <0x40400000 0x1fc00000>; }; qcom,ipa_fws { compatible = "qcom,pil-tz-generic"; qcom,pas-id = <0xf>; qcom,firmware-name = "ipa_fws"; qcom,pil-force-shutdown; memory-region = <&pil_ipa_fw_mem>; }; qcom,venus@5ae0000 { compatible = "qcom,pil-tz-generic"; reg = <0x5ae0000 0x4000>; vdd-supply = <&venus_gdsc>; qcom,proxy-reg-names = "vdd"; qcom,mas-crypto = <&mas_crypto_c0>; clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>, <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; clock-names = "core_clk", "iface_clk", "bus_clk"; qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk"; qcom,pas-id = <9>; qcom,msm-bus,name = "pil-venus"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <63 512 0 0>, <63 512 0 304000>; qcom,proxy-timeout-ms = <100>; qcom,firmware-name = "venus"; memory-region = <&pil_video_mem>; }; cx_ipeak_lm: cx_ipeak@3ed000 { compatible = "qcom,cx-ipeak-v2"; reg = <0x3ed000 0xc00c>; }; ssc_sensors: qcom,msm-ssc-sensors { compatible = "qcom,msm-ssc-sensors"; status = "ok"; }; ddr4_bw_opp_table: ddr4-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */ BW_OPP_ENTRY( 300, 8); /* 2288 MB/s */ BW_OPP_ENTRY( 451, 8); /* 3440 MB/s */ BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */ BW_OPP_ENTRY( 681, 8); /* 5195 MB/s */ BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */ BW_OPP_ENTRY(1017, 8); /* 7759 MB/s */ BW_OPP_ENTRY(1353, 8); /*10322 MB/s */ BW_OPP_ENTRY(1555, 8); /*11863 MB/s */ BW_OPP_ENTRY(1804, 8); /*13763 MB/s */ }; suspendable_ddr4_bw_opp_table: suspendable-ddr4-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 0, 8); /* 0 MB/s */ BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */ BW_OPP_ENTRY( 300, 8); /* 2288 MB/s */ BW_OPP_ENTRY( 451, 8); /* 3440 MB/s */ BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */ BW_OPP_ENTRY( 681, 8); /* 5195 MB/s */ BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */ BW_OPP_ENTRY(1017, 8); /* 7759 MB/s */ BW_OPP_ENTRY(1353, 8); /*10322 MB/s */ BW_OPP_ENTRY(1555, 8); /*11863 MB/s */ BW_OPP_ENTRY(1804, 8); /*13763 MB/s */ }; ddr3_bw_opp_table: ddr3-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */ BW_OPP_ENTRY( 300, 8); /* 2288 MB/s */ BW_OPP_ENTRY( 451, 8); /* 3440 MB/s */ BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */ BW_OPP_ENTRY( 681, 8); /* 5195 MB/s */ BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */ BW_OPP_ENTRY( 931, 8); /* 7102 MB/s */ }; suspendable_ddr3_bw_opp_table: suspendable-ddr3-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 0, 8); /* 0 MB/s */ BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */ BW_OPP_ENTRY( 300, 8); /* 2288 MB/s */ BW_OPP_ENTRY( 451, 8); /* 3440 MB/s */ BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */ BW_OPP_ENTRY( 681, 8); /* 5195 MB/s */ BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */ BW_OPP_ENTRY( 931, 8); /* 7102 MB/s */ }; cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; ddr3-opp { operating-points-v2 = <&ddr3_bw_opp_table>; qcom,ddr-type = ; }; ddr4-opp { operating-points-v2 = <&ddr4_bw_opp_table>; qcom,ddr-type = ; }; }; cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01b8e200 { compatible = "qcom,bimc-bwmon4"; reg = <0x01b8e200 0x100>, <0x01b8e100 0x100>; reg-names = "base", "global_base"; interrupts = ; qcom,mport = <0>; qcom,hw-timer-hz = <19200000>; qcom,target-dev = <&cpu_cpu_ddr_bw>; qcom,count-unit = <0x10000>; }; cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; ddr3-opp { operating-points-v2 = <&ddr3_bw_opp_table>; qcom,ddr-type = ; }; ddr4-opp { operating-points-v2 = <&ddr4_bw_opp_table>; qcom,ddr-type = ; }; }; cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,target-dev = <&cpu0_cpu_ddr_lat>; qcom,cachemiss-ev = <0x17>; qcom,stall-cycle-ev = <0xE7>; ddr3-map { qcom,ddr-type = ; qcom,core-dev-table = < 864000 MHZ_TO_MBPS(200, 8) >, < 1305600 MHZ_TO_MBPS(451, 8) >, < 1804800 MHZ_TO_MBPS(768, 8) >; }; ddr4-map { qcom,ddr-type = ; qcom,core-dev-table = < 864000 MHZ_TO_MBPS( 300, 8) >, < 1305600 MHZ_TO_MBPS( 547, 8) >, < 1420000 MHZ_TO_MBPS( 768, 8) >, < 1804800 MHZ_TO_MBPS(1017, 8) >; }; }; cpu4_cpu_ddr_lat: qcom,cpu4-cpu-ddr-lat { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; ddr3-opp { operating-points-v2 = <&ddr3_bw_opp_table>; qcom,ddr-type = ; }; ddr4-opp { operating-points-v2 = <&ddr4_bw_opp_table>; qcom,ddr-type = ; }; }; cpu4_cpu_ddr_latmon: qcom,cpu4-cpu-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,target-dev = <&cpu4_cpu_ddr_lat>; qcom,cachemiss-ev = <0x17>; qcom,stall-cycle-ev = <0x24>; ddr3-map { qcom,ddr-type = ; qcom,core-dev-table = < 1056000 MHZ_TO_MBPS(200, 8) >, < 1401600 MHZ_TO_MBPS(451, 8) >, < 1804800 MHZ_TO_MBPS(768, 8) >, < 2016000 MHZ_TO_MBPS(931, 8) >; }; ddr4-map { qcom,ddr-type = ; qcom,core-dev-table = < 902400 MHZ_TO_MBPS( 451, 8) >, < 1401600 MHZ_TO_MBPS(1017, 8) >, < 1804800 MHZ_TO_MBPS(1555, 8) >, < 2016000 MHZ_TO_MBPS(1804, 8) >; }; }; cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; ddr3-opp { operating-points-v2 = <&ddr3_bw_opp_table>; qcom,ddr-type = ; }; ddr4-opp { operating-points-v2 = <&ddr4_bw_opp_table>; qcom,ddr-type = ; }; }; cpu0_computemon: qcom,cpu0-computemon { compatible = "qcom,arm-cpu-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; ddr3-map { qcom,ddr-type = ; qcom,core-dev-table = < 614400 MHZ_TO_MBPS( 200, 8) >, < 1305600 MHZ_TO_MBPS( 451, 8) >, < 1804800 MHZ_TO_MBPS( 768, 8) >; }; ddr4-map { qcom,ddr-type = ; qcom,core-dev-table = < 614400 MHZ_TO_MBPS( 300, 8) >, < 1017600 MHZ_TO_MBPS( 451, 8) >, < 1420000 MHZ_TO_MBPS( 547, 8) >, < 1804800 MHZ_TO_MBPS( 768, 8) >; }; }; cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; ddr3-opp { operating-points-v2 = <&ddr3_bw_opp_table>; qcom,ddr-type = ; }; ddr4-opp { operating-points-v2 = <&ddr4_bw_opp_table>; qcom,ddr-type = ; }; }; cpu4_computemon: qcom,cpu4-computemon { compatible = "qcom,arm-cpu-mon"; qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; ddr3-map { qcom,ddr-type = ; qcom,core-dev-table = < 1056000 MHZ_TO_MBPS( 200, 8) >, < 1401600 MHZ_TO_MBPS( 451, 8) >, < 1804800 MHZ_TO_MBPS( 768, 8) >, < 2016000 MHZ_TO_MBPS( 931, 8) >; }; ddr4-map { qcom,ddr-type = ; qcom,core-dev-table = < 902400 MHZ_TO_MBPS( 300, 8) >, < 1056000 MHZ_TO_MBPS( 547, 8) >, < 1401680 MHZ_TO_MBPS( 768, 8) >, < 1804800 MHZ_TO_MBPS(1017, 8) >, < 2016000 MHZ_TO_MBPS(1804, 8) >; }; }; demux { compatible = "qcom,demux"; }; qfprom: qfprom@1b46018 { compatible = "qcom,qfprom"; reg = <0x1b46018 0x4>; #address-cells = <1>; #size-cells = <1>; read-only; ranges; }; }; #include "pmi632.dtsi" #include "pm6125.dtsi" #include "trinket-qupv3.dtsi" #include "trinket-pinctrl.dtsi" #include "trinket-ion.dtsi" #include "pm6125-rpm-regulator.dtsi" #include "trinket-regulator.dtsi" #include "trinket-gdsc.dtsi" #include "trinket-usb.dtsi" #include "trinket-camera.dtsi" #include "msm-arm-smmu-trinket.dtsi" #include "trinket-qupv3.dtsi" #include "trinket-coresight.dtsi" #include "trinket-vidc.dtsi" #include "trinket-pm.dtsi" #include "trinket-gpu.dtsi" #include "trinket-bus.dtsi" #include "trinket-sde-pll.dtsi" #include "trinket-sde.dtsi" #include "msm-rdbg.dtsi" &pm6125_vadc { pinctrl-names = "default"; pinctrl-0 = <&camera_therm_default &emmc_therm_default>; rf_pa0_therm { reg = ; label = "rf_pa0_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; quiet_therm { reg = ; label = "quiet_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; camera_flash_therm { reg = ; label = "camera_flash_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; emmc_ufs_therm { reg = ; label = "emmc_ufs_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; }; &pm6125_gpios { camera_therm { camera_therm_default: camera_therm_default { pins = "gpio3"; bias-high-impedance; }; }; emmc_therm { emmc_therm_default: emmc_therm_default { pins = "gpio6"; bias-high-impedance; }; }; }; &spmi_bus { qcom,pm6125@0 { pm6125_adc_tm_iio: adc_tm@3400 { compatible = "qcom,adc-tm5-iio"; reg = <0x3400 0x100>; #thermal-sensor-cells = <1>; #address-cells = <1>; #size-cells = <0>; io-channels = <&pm6125_vadc ADC_GPIO1_PU2>, <&pm6125_vadc ADC_GPIO3_PU2>; camera_flash_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; emmc_ufs_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; }; }; }; &pm6125_adc_tm { io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>, <&pm6125_vadc ADC_AMUX_THM2_PU2>, <&pm6125_vadc ADC_XO_THERM_PU2>; /* Channel nodes */ rf_pa0_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; quiet_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; xo_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; }; &pmi632_vadc { pinctrl-names = "default"; pinctrl-0 = <&conn_therm_default &skin_therm_default>; xo_therm { status = "disabled"; }; bat_therm { qcom,lut-index = <1>; }; bat_therm_30k { qcom,lut-index = <1>; }; bat_therm_400k { qcom,lut-index = <1>; }; conn_therm { reg = ; label = "conn_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; skin_therm { reg = ; label = "skin_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; }; &pmi632_gpios { conn_therm { conn_therm_default: conn_therm_default { pins = "gpio1"; bias-high-impedance; }; }; skin_therm { skin_therm_default: skin_therm_default { pins = "gpio3"; bias-high-impedance; }; }; }; &pmi632_adc_tm { io-channels = <&pmi632_vadc ADC_GPIO1_PU2>, <&pmi632_vadc ADC_VBAT_SNS>, <&pmi632_vadc ADC_GPIO2_PU2>; /* Channel nodes */ conn_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; vbat_sns { reg = ; qcom,kernel-client; qcom,scale-type = <0>; qcom,prescaling = <3>; }; skin_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; }; &ufs_phy_gdsc { status = "ok"; }; &usb30_prim_gdsc { status = "ok"; }; &camss_cpp_gdsc { status = "ok"; }; &camss_top_gdsc { status = "ok"; }; &camss_vfe0_gdsc { status = "ok"; }; &camss_vfe1_gdsc { status = "ok"; }; &hlos1_vote_turing_mmu_tbu1_gdsc { status = "ok"; }; &hlos1_vote_turing_mmu_tbu0_gdsc { status = "ok"; }; &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc { status = "ok"; }; &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc { status = "ok"; }; &mdss_core_gdsc { status = "ok"; }; &gpu_cx_gdsc { status = "ok"; }; &gpu_gx_gdsc { status = "ok"; }; &vcodec0_gdsc { qcom,support-hw-trigger; status = "ok"; }; &venus_gdsc { status = "ok"; }; &qupv3_se4_2uart { status = "ok"; }; &qupv3_se9_4uart { status = "ok"; }; &qupv3_se1_i2c { status = "ok"; fsa4480: fsa4480@43 { compatible = "qcom,fsa4480-i2c"; reg = <0x43>; pinctrl-names = "default"; pinctrl-0 = <&fsa_usbc_ana_en>; }; }; &msm_vidc { qcom,cx-ipeak-data = <&cx_ipeak_lm 6>; qcom,clock-freq-threshold = <460000000>; }; #include "trinket-audio.dtsi" #include "trinket-thermal.dtsi" &soc { icnss: qcom,icnss@C800000 { compatible = "qcom,icnss"; reg = <0xC800000 0x800000>, <0xa0000000 0x10000000>, <0xb0000000 0x10000>; reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; iommus = <&apps_smmu 0x80 0x1>; interrupts = <0 358 0 /* CE0 */ >, <0 359 0 /* CE1 */ >, <0 360 0 /* CE2 */ >, <0 361 0 /* CE3 */ >, <0 362 0 /* CE4 */ >, <0 363 0 /* CE5 */ >, <0 364 0 /* CE6 */ >, <0 365 0 /* CE7 */ >, <0 366 0 /* CE8 */ >, <0 367 0 /* CE9 */ >, <0 368 0 /* CE10 */ >, <0 369 0 /* CE11 */ >; qcom,wlan-msa-memory = <0x100000>; qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; vdd-cx-mx-supply = <&L8A>; vdd-1.8-xo-supply = <&L16A>; vdd-1.3-rfa-supply = <&L17A>; vdd-3.3-ch0-supply = <&L23A>; qcom,vdd-cx-mx-config = <640000 640000>; qcom,vdd-3.3-ch0-config = <3000000 3312000>; qcom,icnss-adc_tm = <&pmi632_adc_tm>; io-channels = <&pmi632_vadc ADC_VBAT_SNS>; io-channel-names = "icnss"; qcom,smp2p_map_wlan_1_in { interrupts-extended = <&smp2p_wlan_1_in 0 0>, <&smp2p_wlan_1_in 1 0>; interrupt-names = "qcom,smp2p-force-fatal-error", "qcom,smp2p-early-crash-ind"; }; }; }; &qupv3_se1_i2c { status="ok"; #include "pm8008.dtsi" }; &tlmm { pm8008_active: pm8008_active { mux { pins = "gpio49"; function = "gpio"; }; config { pins = "gpio49"; bias-pull-up; output-high; drive-strength = <2>; }; }; }; &pm8008_gpios { gpio1_active { pm8008_gpio1_active: pm8008_gpio1_active { pins = "gpio1"; function = "normal"; power-source = <1>; bias-disable; input-enable; }; }; }; &pm8008_chip { pinctrl-names = "default"; pinctrl-0 = <&pm8008_active>; }; &pm8008_regulators { vdd_l1_l2-supply = <&S6A>; }; &pm8008_9 { /* GPIO1 pinctrl config */ pinctrl-names = "default"; pinctrl-0 = <&pm8008_gpio1_active>; }; &L1P { regulator-max-microvolt = <1200000>; qcom,min-dropout-voltage = <100000>; }; &L2P { regulator-max-microvolt = <1104000>; qcom,min-dropout-voltage = <100000>; }; &L3P { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; &L4P { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; &L5P { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; &L6P { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; }; &L7P { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; };