/* Copyright (c) 2018-2020, The Linux Foundation.All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include "skeleton64.dtsi" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) #define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} / { model = "Qualcomm Technologies, Inc. SM6150"; compatible = "qcom,sm6150"; qcom,msm-name = "SM6150"; qcom,msm-id = <355 0x0>; interrupt-parent = <&pdc>; aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ serial0 = &qupv3_se0_2uart; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ spi0 = &qupv3_se4_spi; i2c0 = &qupv3_se5_i2c; i2c1 = &qupv3_se1_i2c; i2c2 = &qupv3_se3_i2c; hsuart0 = &qupv3_se7_4uart; hsuart1 = &qupv3_se4_2uart; swr0 = &swr0; swr1 = &swr1; swr2 = &swr2; }; cpus { #address-cells = <2>; #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "arm,arch-cache"; cache-level = <3>; }; }; L1_I_0: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x8800>; }; L1_D_0: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9000>; }; L2_TLB_0: l2-tlb { qcom,dump-size = <0x5000>; }; }; CPU1: cpu@100 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; next-level-cache = <&L2_100>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; next-level-cache = <&L3_0>; }; L1_I_100: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x8800>; }; L1_D_100: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9000>; }; L2_TLB_100: l1-tlb { qcom,dump-size = <0x5000>; }; }; CPU2: cpu@200 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; next-level-cache = <&L2_200>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; next-level-cache = <&L3_0>; }; L1_I_200: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x8800>; }; L1_D_200: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9000>; }; L2_TLB_200: l1-tlb { qcom,dump-size = <0x5000>; }; }; CPU3: cpu@300 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x300>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; next-level-cache = <&L2_300>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; next-level-cache = <&L3_0>; }; L1_I_300: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x8800>; }; L1_D_300: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9000>; }; L2_TLB_300: l1-tlb { qcom,dump-size = <0x5000>; }; }; CPU4: cpu@400 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; next-level-cache = <&L2_400>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; next-level-cache = <&L3_0>; }; L1_I_400: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x8800>; }; L1_D_400: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9000>; }; L2_TLB_400: l1-tlb { qcom,dump-size = <0x5000>; }; }; CPU5: cpu@500 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; next-level-cache = <&L2_500>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; next-level-cache = <&L3_0>; }; L1_I_500: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x8800>; }; L1_D_500: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x9000>; }; L2_TLB_500: l1-tlb { qcom,dump-size = <0x5000>; }; }; CPU6: cpu@600 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1740>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; next-level-cache = <&L2_600>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; next-level-cache = <&L3_0>; qcom,dump-size = <0x48000>; }; L1_I_600: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x11000>; }; L1_D_600: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x12000>; }; L1_ITLB_600: l1-itlb { qcom,dump-size = <0x300>; }; L1_DTLB_600: l1-dtlb { qcom,dump-size = <0x480>; }; L2_TLB_600: l2-tlb { qcom,dump-size = <0x7800>; }; }; CPU7: cpu@700 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1740>; sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; next-level-cache = <&L2_700>; qcom,lmh-dcvs = <&lmh_dcvs1>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; next-level-cache = <&L3_0>; qcom,dump-size = <0x48000>; }; L1_I_700: l1-icache { compatible = "arm,arch-cache"; qcom,dump-size = <0x11000>; }; L1_D_700: l1-dcache { compatible = "arm,arch-cache"; qcom,dump-size = <0x12000>; }; L1_ITLB_700: l1-itlb { qcom,dump-size = <0x300>; }; L1_DTLB_700: l1-dtlb { qcom,dump-size = <0x480>; }; L2_TLB_700: l2-tlb { qcom,dump-size = <0x7800>; }; }; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; core4 { cpu = <&CPU4>; }; core5 { cpu = <&CPU5>; }; }; cluster1 { core0 { cpu = <&CPU6>; }; core1 { cpu = <&CPU7>; }; }; }; }; energy_costs: energy-costs { compatible = "sched-energy"; CPU_COST_0: core-cost0 { busy-cost-data = < 300000 24 576000 25 748800 31 1017600 54 1209600 78 1363200 105 1516800 116 1593600 139 1708800 168 1804800 178 >; idle-cost-data = < 16 12 8 6 >; }; CPU_COST_1: core-cost1 { busy-cost-data = < 300000 180 652800 236 768000 273 979200 446 1017600 462 1209600 662 1363200 894 1516800 989 1708800 1276 1900800 1652 2016000 2040 2112000 2242 2208000 2713 >; idle-cost-data = < 100 80 60 40 >; }; CLUSTER_COST_0: cluster-cost0 { busy-cost-data = < 300000 8 576000 8 748800 9 1017600 12 1209600 15 1363200 18 1516800 21 1593600 22 1708800 23 1804800 24 >; idle-cost-data = < 4 3 2 1 >; }; CLUSTER_COST_1: cluster-cost1 { busy-cost-data = < 300000 28 652800 35 768000 36 979200 48 1017600 59 1209600 73 1363200 86 1516800 88 1708800 96 1900800 103 2016000 107 2112000 112 2208000 120 >; idle-cost-data = < 4 3 2 1 >; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; chosen { bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; }; soc: soc { }; firmware: firmware { android { compatible = "android,firmware"; vbmeta { compatible = "android,vbmeta"; parts = "vbmeta,boot,system,vendor,dtbo"; }; fstab { compatible = "android,fstab"; vendor { compatible = "android,vendor"; dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; fsmgr_flags = "wait,slotselect,avb"; status = "ok"; }; }; }; }; reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; hyp_region: hyp_region@85700000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x85700000 0 0x600000>; }; xbl_aop_mem: xbl_aop_mem@85d00000 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x85d00000 0x0 0x240000>; }; sec_apps_mem: sec_apps_region@85fff000 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x85fff000 0x0 0x1000>; }; smem_region: smem@86000000 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x86000000 0x0 0x200000>; }; removed_region: removed_region@86200000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x86200000 0 0x2d00000>; }; pil_camera_mem: camera_region@8ab00000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x8ab00000 0 0x500000>; }; pil_modem_mem: modem_region@8b000000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x8b000000 0 0x8400000>; }; pil_video_mem: pil_video_region@93400000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x93400000 0 0x500000>; }; wlan_msa_mem: wlan_msa_region@93900000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x93900000 0 0x200000>; }; pil_cdsp_mem: cdsp_regions@93b00000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x93b00000 0 0x1e00000>; }; pil_adsp_mem: pil_adsp_region@95900000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x95900000 0 0x1e00000>; }; pil_ipa_fw_mem: ips_fw_region@0x97700000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x97700000 0 0x10000>; }; pil_ipa_gsi_mem: ipa_gsi_region@0x97710000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x97710000 0 0x5000>; }; pil_gpu_mem: gpu_region@0x97715000 { compatible = "removed-dma-pool"; no-map; reg = <0 0x97715000 0 0x2000>; }; qseecom_mem: qseecom_region@0x9e400000 { compatible = "shared-dma-pool"; no-map; reg = <0 0x9e400000 0 0x1400000>; }; cdsp_sec_mem: cdsp_sec_regions@0x9f800000 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x9f800000 0x0 0x1e00000>; }; adsp_mem: adsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; size = <0 0x800000>; }; sdsp_mem: sdsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; size = <0 0x400000>; }; qseecom_ta_mem: qseecom_ta_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; size = <0 0x1000000>; }; sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */ reusable; alignment = <0 0x400000>; size = <0 0x800000>; }; secure_display_memory: secure_display_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; size = <0 0x8c00000>; }; cont_splash_memory: cont_splash_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x0f00000>; label = "cont_splash_region"; }; dfps_data_memory: dfps_data_region@9cf00000 { reg = <0x0 0x9cf00000 0x0 0x0100000>; label = "dfps_data_region"; }; disp_rdump_memory: disp_rdump_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x0f00000>; label = "disp_rdump_region"; }; dump_mem: mem_dump_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; size = <0 0x2400000>; }; /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; size = <0 0x2800000>; linux,cma-default; }; }; }; &soc { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; #redistributor-regions = <1>; redistributor-stride = <0x0 0x20000>; reg = <0x17a00000 0x10000>, /* GICD */ <0x17a60000 0x100000>; /* GICR * 8 */ interrupts = <1 9 4>; interrupt-parent = <&intc>; }; pdc: interrupt-controller@b220000{ compatible = "qcom,pdc-sm6150"; reg = <0xb220000 0x400>; #interrupt-cells = <3>; interrupt-parent = <&intc>; interrupt-controller; }; qcom,memshare { compatible = "qcom,memshare"; qcom,client_1 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x0>; qcom,client-id = <0>; qcom,allocate-boot-time; label = "modem"; }; qcom,client_2 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x0>; qcom,client-id = <2>; label = "modem"; }; mem_client_3_size: qcom,client_3 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x500000>; qcom,client-id = <1>; qcom,allocate-on-request; label = "modem"; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <1 1 0xf08>, <1 2 0xf08>, <1 3 0xf08>, <1 0 0xf08>; clock-frequency = <19200000>; }; timer@0x17c20000{ #address-cells = <1>; #size-cells = <1>; ranges; compatible = "arm,armv7-timer-mem"; reg = <0x17c20000 0x1000>; clock-frequency = <19200000>; frame@0x17c21000 { frame-number = <0>; interrupts = <0 8 0x4>, <0 6 0x4>; reg = <0x17c21000 0x1000>, <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <0 9 0x4>; reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <0 10 0x4>; reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <0 11 0x4>; reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <0 12 0x4>; reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <0 13 0x4>; reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <0 14 0x4>; reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; clocks { sleep_clk: sleep-clk { compatible = "fixed-clock"; clock-frequency = <32000>; clock-output-names = "chip_sleep_clk"; #clock-cells = <1>; }; scc_pll_out_aux2: scc_pll_out_aux2 { compatible = "fixed-clock"; clock-frequency = <600000000>; clock-output-names = "scc_pll_out_aux2"; #clock-cells = <0>; }; scc_pll_out_aux: scc_pll_out_aux { compatible = "fixed-factor-clock"; clock-output-names = "scc_pll_out_aux"; clocks = <&scc_pll_out_aux2>; clock-mult = <1>; clock-div = <2>; #clock-cells = <0>; }; }; clock_rpmh: qcom,rpmhclk { compatible = "qcom,rpmh-clk-sm6150"; mboxes = <&apps_rsc 0>; mbox-names = "apps"; #clock-cells = <1>; }; clock_aop: qcom,aopclk { compatible = "qcom,aop-qmp-clk"; #clock-cells = <1>; mboxes = <&qmp_aop 0>; mbox-names = "qdss_clk"; }; clock_gcc: qcom,gcc@100000 { compatible = "qcom,gcc-sm6150", "syscon"; reg = <0x100000 0x1f0000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; protected-clocks = , , , , , , ; #clock-cells = <1>; #reset-cells = <1>; }; clock_videocc: qcom,videocc@ab00000 { compatible = "qcom,videocc-sm6150", "syscon"; reg = <0xab00000 0x10000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; #clock-cells = <1>; #reset-cells = <1>; }; clock_camcc: qcom,camcc@ad00000 { compatible = "qcom,camcc-sm6150", "syscon"; reg = <0xad00000 0x10000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>; #clock-cells = <1>; #reset-cells = <1>; qcom,cam_cc_csi0phytimer_clk_src-opp-handle = <&cam_csiphy0>; qcom,cam_cc_csi1phytimer_clk_src-opp-handle = <&cam_csiphy1>; qcom,cam_cc_csi2phytimer_clk_src-opp-handle = <&cam_csiphy2>; qcom,cam_cc_cci_clk_src-opp-handle = <&cam_cci>; qcom,cam_cc_ife_0_csid_clk_src-opp-handle = <&cam_csid0>; qcom,cam_cc_ife_0_clk_src-opp-handle = <&cam_vfe0>; qcom,cam_cc_ife_1_csid_clk_src-opp-handle = <&cam_csid1>; qcom,cam_cc_ife_1_clk_src-opp-handle = <&cam_vfe1>; qcom,cam_cc_ife_lite_csid_clk_src-opp-handle = <&cam_csid_lite>; qcom,cam_cc_ife_lite_clk_src-opp-handle = <&cam_vfe_lite>; qcom,cam_cc_icp_clk_src-opp-handle = <&cam_a5>; qcom,cam_cc_ipe_0_clk_src-opp-handle = <&cam_ipe0>; qcom,cam_cc_bps_clk_src-opp-handle = <&cam_bps>; }; clock_dispcc: qcom,dispcc@af00000 { compatible = "qcom,dispcc-sm6150", "syscon"; reg = <0xaf00000 0x20000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; #clock-cells = <1>; #reset-cells = <1>; }; clock_gpucc: qcom,gpupcc@5090000 { compatible = "qcom,gpucc-sm6150", "syscon"; reg = <0x5090000 0x9000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>; #clock-cells = <1>; #reset-cells = <1>; qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>; }; clock_scc: qcom,scc@62b10000 { compatible = "qcom,scc-sm6150"; reg = <0x62b10000 0x30000>; vdd_scc_cx-supply = <&VDD_CX_LEVEL>; #clock-cells = <1>; status = "disabled"; }; cpucc_debug: syscon@182a0018 { compatible = "syscon"; reg = <0x182a0018 0x4>; }; mccc_debug: syscon@90b0000 { compatible = "syscon"; reg = <0x90b0000 0x1000>; }; clock_cpucc: qcom,cpucc@18321000 { compatible = "qcom,clk-cpu-osm-sm6150"; reg = <0x18321000 0x1400>, <0x18323000 0x1400>, <0x18325800 0x1400>; reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base"; l3-devs = <&cpu0_cpu_l3_lat &cpu6_cpu_l3_lat &cdsp_cdsp_l3_lat &msm_gpu>; #clock-cells = <1>; }; clock_debugcc: qcom,cc-debug { compatible = "qcom,debugcc-sm6150"; qcom,gcc = <&clock_gcc>; qcom,videocc = <&clock_videocc>; qcom,camcc = <&clock_camcc>; qcom,dispcc = <&clock_dispcc>; qcom,gpucc = <&clock_gpucc>; qcom,cpucc = <&cpucc_debug>; qcom,mccc = <&mccc_debug>; clock-names = "cxo"; clocks = <&clock_rpmh RPMH_CXO_CLK>; #clock-cells = <1>; }; cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; qcom,irq-is-percpu; interrupts = <1 5 4>; }; dsu_pmu@0 { compatible = "arm,dsu-pmu"; interrupts = ; cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; }; qcom,msm-imem@146aa000 { compatible = "qcom,msm-imem"; reg = <0x146aa000 0x1000>; ranges = <0x0 0x146aa000 0x1000>; #address-cells = <1>; #size-cells = <1>; mem_dump_table@10 { compatible = "qcom,msm-imem-mem_dump_table"; reg = <0x10 8>; }; restart_reason@65c { compatible = "qcom,msm-imem-restart_reason"; reg = <0x65c 4>; }; dload_type@1c { compatible = "qcom,msm-imem-dload-type"; reg = <0x1c 0x4>; }; boot_stats@6b0 { compatible = "qcom,msm-imem-boot_stats"; reg = <0x6b0 32>; }; kaslr_offset@6d0 { compatible = "qcom,msm-imem-kaslr_offset"; reg = <0x6d0 12>; }; pil@94c { compatible = "qcom,msm-imem-pil"; reg = <0x94c 200>; }; diag_dload@c8 { compatible = "qcom,msm-imem-diag-dload"; reg = <0xc8 200>; }; upload_cause@66c { compatible = "qcom,msm-imem-upload_cause"; reg = <0x66c 4>; }; }; restart@c264000 { compatible = "qcom,pshold"; reg = <0xc264000 0x4>, <0x1fd3000 0x4>; reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; qcom,mpm2-sleep-counter@0xc221000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0xc221000 0x1000>; clock-frequency = <32768>; }; qcom,sps { compatible = "qcom,msm-sps-4k"; qcom,pipe-attr-ee; }; gpi_dma0: qcom,gpi-dma@0x800000 { #dma-cells = <5>; compatible = "qcom,gpi-dma"; reg = <0x800000 0x60000>; reg-names = "gpi-top"; interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>, <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>; qcom,ev-factor = <2>; qcom,max-num-gpii = <8>; qcom,gpii-mask = <0x0f>; iommus = <&apps_smmu 0x00d6 0x0>; qcom,smmu-cfg = <0x1>; qcom,iova-range = <0x0 0x100000 0x0 0x100000>; status = "ok"; }; gpi_dma1: qcom,gpi-dma@0xa00000 { #dma-cells = <5>; compatible = "qcom,gpi-dma"; reg = <0xa00000 0x60000>; reg-names = "gpi-top"; interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>, <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>; qcom,ev-factor = <2>; qcom,max-num-gpii = <8>; qcom,gpii-mask = <0x0f>; qcom,smmu-cfg = <0x1>; qcom,iova-range = <0x0 0x100000 0x0 0x100000>; iommus = <&apps_smmu 0x0376 0x0>; status = "ok"; }; aop-msg-client { compatible = "qcom,debugfs-qmp-client"; mboxes = <&qmp_aop 0>; mbox-names = "aop"; }; qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; }; wdog: qcom,wdt@17c10000{ compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; reg-names = "wdt-base"; interrupts = <0 0 0>, <0 1 0>; qcom,bark-time = <11000>; qcom,pet-time = <9360>; qcom,ipi-ping; qcom,wakeup-enable; qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100 0x10100 0x10100 0x25900 0x25900>; }; qcom,chd_sliver { compatible = "qcom,core-hang-detect"; label = "silver"; qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058 0x18040058 0x18050058>; qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060 0x18040060 0x18050060>; }; qcom,chd_gold { compatible = "qcom,core-hang-detect"; label = "gold"; qcom,threshold-arr = <0x18060058 0x18070058>; qcom,config-arr = <0x18060060 0x18070060>; }; kryo-erp { compatible = "arm,arm64-kryo-cpu-erp"; interrupts = <1 6 4>, <0 35 4>; interrupt-names = "l1-l2-faultirq", "l3-scu-faultirq"; }; qcom,ghd { compatible = "qcom,gladiator-hang-detect-v3"; qcom,threshold-arr = <0x17e0041C>; qcom,config-reg = <0x17e00434>; }; cpuss_dump { compatible = "qcom,cpuss-dump"; qcom,l1_i_cache0 { qcom,dump-node = <&L1_I_0>; qcom,dump-id = <0x60>; }; qcom,l1_i_cache100 { qcom,dump-node = <&L1_I_100>; qcom,dump-id = <0x61>; }; qcom,l1_i_cache200 { qcom,dump-node = <&L1_I_200>; qcom,dump-id = <0x62>; }; qcom,l1_i_cache300 { qcom,dump-node = <&L1_I_300>; qcom,dump-id = <0x63>; }; qcom,l1_i_cache400 { qcom,dump-node = <&L1_I_400>; qcom,dump-id = <0x64>; }; qcom,l1_i_cache500 { qcom,dump-node = <&L1_I_500>; qcom,dump-id = <0x65>; }; qcom,l1_i_cache600 { qcom,dump-node = <&L1_I_600>; qcom,dump-id = <0x66>; }; qcom,l1_i_cache700 { qcom,dump-node = <&L1_I_700>; qcom,dump-id = <0x67>; }; qcom,l1_d_cache0 { qcom,dump-node = <&L1_D_0>; qcom,dump-id = <0x80>; }; qcom,l1_d_cache100 { qcom,dump-node = <&L1_D_100>; qcom,dump-id = <0x81>; }; qcom,l1_d_cache200 { qcom,dump-node = <&L1_D_200>; qcom,dump-id = <0x82>; }; qcom,l1_d_cache300 { qcom,dump-node = <&L1_D_300>; qcom,dump-id = <0x83>; }; qcom,l1_d_cache400 { qcom,dump-node = <&L1_D_400>; qcom,dump-id = <0x84>; }; qcom,l1_d_cache500 { qcom,dump-node = <&L1_D_500>; qcom,dump-id = <0x85>; }; qcom,l1_d_cache600 { qcom,dump-node = <&L1_D_600>; qcom,dump-id = <0x86>; }; qcom,l1_d_cache700 { qcom,dump-node = <&L1_D_700>; qcom,dump-id = <0x87>; }; qcom,l1_i_tlb_dump600 { qcom,dump-node = <&L1_ITLB_600>; qcom,dump-id = <0x26>; }; qcom,l1_i_tlb_dump700 { qcom,dump-node = <&L1_ITLB_700>; qcom,dump-id = <0x27>; }; qcom,l1_d_tlb_dump600 { qcom,dump-node = <&L1_DTLB_600>; qcom,dump-id = <0x46>; }; qcom,l1_d_tlb_dump700 { qcom,dump-node = <&L1_DTLB_700>; qcom,dump-id = <0x47>; }; qcom,l2_cache_dump600 { qcom,dump-node = <&L2_600>; qcom,dump-id = <0xc6>; }; qcom,l2_cache_dump700 { qcom,dump-node = <&L2_700>; qcom,dump-id = <0xc7>; }; qcom,l2_tlb_dump0 { qcom,dump-node = <&L2_TLB_0>; qcom,dump-id = <0x120>; }; qcom,l2_tlb_dump100 { qcom,dump-node = <&L2_TLB_100>; qcom,dump-id = <0x121>; }; qcom,l2_tlb_dump200 { qcom,dump-node = <&L2_TLB_200>; qcom,dump-id = <0x122>; }; qcom,l2_tlb_dump300 { qcom,dump-node = <&L2_TLB_300>; qcom,dump-id = <0x123>; }; qcom,l2_tlb_dump400 { qcom,dump-node = <&L2_TLB_400>; qcom,dump-id = <0x124>; }; qcom,l2_tlb_dump500 { qcom,dump-node = <&L2_TLB_500>; qcom,dump-id = <0x125>; }; qcom,l2_tlb_dump600 { qcom,dump-node = <&L2_TLB_600>; qcom,dump-id = <0x126>; }; qcom,l2_tlb_dump700 { qcom,dump-node = <&L2_TLB_700>; qcom,dump-id = <0x127>; }; qcom,llcc1_d_cache { qcom,dump-node = <&LLCC_1>; qcom,dump-id = <0x140>; }; }; mem_dump { compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; rpmh { qcom,dump-size = <0x2000000>; qcom,dump-id = <0xec>; }; rpm_sw { qcom,dump-size = <0x28000>; qcom,dump-id = <0xea>; }; pmic { qcom,dump-size = <0x10000>; qcom,dump-id = <0xe4>; }; fcm { qcom,dump-size = <0x8400>; qcom,dump-id = <0xee>; }; tmc_etf { qcom,dump-size = <0x8000>; qcom,dump-id = <0xf0>; }; etf_swao { qcom,dump-size = <0x8000>; qcom,dump-id = <0xf1>; }; etr_reg { qcom,dump-size = <0x1000>; qcom,dump-id = <0x100>; }; etf_reg { qcom,dump-size = <0x1000>; qcom,dump-id = <0x101>; }; etfswao_reg { qcom,dump-size = <0x1000>; qcom,dump-id = <0x102>; }; misc_data { qcom,dump-size = <0x1000>; qcom,dump-id = <0xe8>; }; }; apps_rsc: mailbox@18220000 { compatible = "qcom,tcs-drv"; label = "apps_rsc"; reg = <0x18220000 0x100>, <0x18220d00 0x3000>; interrupts = <0 5 0>; #mbox-cells = <1>; qcom,drv-id = <2>; qcom,tcs-config = , , , ; }; disp_rsc: mailbox@af20000 { compatible = "qcom,tcs-drv"; label = "display_rsc"; reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>; interrupts = <0 129 0>; #mbox-cells = <1>; qcom,drv-id = <0>; qcom,tcs-config = , , , ; }; system_pm { compatible = "qcom,system-pm"; mboxes = <&apps_rsc 0>; }; cmd_db: qcom,cmd-db@c3f000c { compatible = "qcom,cmd-db"; reg = <0xc3f000c 8>; }; dcc: dcc_v2@10a2000 { compatible = "qcom,dcc-v2"; reg = <0x10a2000 0x1000>, <0x10ae000 0x2000>; reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x6000>; }; qcom,llcc@9200000 { compatible = "qcom,llcc-core", "syscon", "simple-mfd"; reg = <0x9200000 0x450000>; reg-names = "llcc_base"; qcom,llcc-banks-off = <0x0>; qcom,llcc-broadcast-off = <0x400000>; llcc: qcom,sm6150-llcc { compatible = "qcom,sm6150-llcc"; #cache-cells = <1>; max-slices = <32>; cap-based-alloc-and-pwr-collapse; }; qcom,llcc-perfmon { compatible = "qcom,llcc-perfmon"; clocks = <&clock_aop QDSS_CLK>; clock-names = "qdss_clk"; }; qcom,llcc-erp { compatible = "qcom,llcc-erp"; }; qcom,llcc-amon { compatible = "qcom,llcc-amon"; }; LLCC_1: llcc_1_dcache { qcom,dump-size = <0x6c000>; }; }; sdcc1_ice: sdcc1ice@7C8000{ compatible = "qcom,ice"; reg = <0x7C8000 0x8000>; qcom,enable-ice-clk; clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk"; clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>, <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>, <&clock_gcc GCC_SDCC1_AHB_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>; qcom,op-freq-hz = <300000000>, <0>, <0>, <0>; qcom,msm-bus,name = "sdcc_ice_noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 757 0 0>, /* No vote */ <1 757 1000 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "MAX"; qcom,instance-type = "sdcc"; }; sdhc_1: sdhci@7c4000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7C8000 0x8000>; reg-names = "hc_mem", "cmdq_mem", "cmdq_ice"; interrupts = <0 641 0>, <0 644 0>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <8>; qcom,large-address-bus; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>; qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; qcom,devfreq,freq-table = <50000000 200000000>; qcom,msm-bus,name = "sdhc1"; qcom,msm-bus,num-cases = <9>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = /* No vote */ <78 512 0 0>, <1 606 0 0>, /* 400 KB/s*/ <78 512 1046 1600>, <1 606 1600 1600>, /* 20 MB/s */ <78 512 52286 80000>, <1 606 80000 80000>, /* 25 MB/s */ <78 512 65360 100000>, <1 606 100000 100000>, /* 50 MB/s */ <78 512 130718 200000>, <1 606 133320 133320>, /* 100 MB/s */ <78 512 130718 200000>, <1 606 150000 150000>, /* 200 MB/s */ <78 512 261438 400000>, <1 606 300000 300000>, /* 400 MB/s */ <78 512 261438 2718822>, <1 606 300000 1359411>, /* Max. bandwidth */ <78 512 1338562 4096000>, <1 606 1338562 4096000>; qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100750000 200000000 400000000 4294967295>; /* PM QoS */ qcom,pm-qos-irq-type = "affine_irq"; qcom,pm-qos-irq-latency = <67 67>; qcom,pm-qos-cpu-groups = <0x3f 0xc0>; qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>; qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>; clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>, <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface_clk", "core_clk", "ice_core_clk"; qcom,ice-clk-rates = <300000000 75000000>; /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x000F642C 0x0 0x0 0x00010800 0x80040868>; qcom,nonremovable; status = "disabled"; }; sdhc_2: sdhci@8804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x8804000 0x1000>; reg-names = "hc_mem"; interrupts = <0 204 0>, <0 222 0>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <4>; qcom,large-address-bus; qcom,clk-rates = <300000 400000 20000000 25000000 50000000 100000000 202000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; qcom,devfreq,freq-table = <50000000 202000000>; qcom,msm-bus,name = "sdhc2"; qcom,msm-bus,num-cases = <8>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = /* No vote */ <81 512 0 0>, <1 608 0 0>, /* 400 KB/s*/ <81 512 1046 1600>, <1 608 1600 1600>, /* 20 MB/s */ <81 512 52286 80000>, <1 608 80000 80000>, /* 25 MB/s */ <81 512 65360 100000>, <1 608 100000 100000>, /* 50 MB/s */ <81 512 130718 200000>, <1 608 133320 133320>, /* 100 MB/s */ <81 512 261438 200000>, <1 608 150000 150000>, /* 200 MB/s */ <81 512 261438 400000>, <1 608 300000 300000>, /* Max. bandwidth */ <81 512 1338562 4096000>, <1 608 1338562 4096000>; qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100750000 200000000 4294967295>; qcom,restore-after-cx-collapse; /* PM QoS */ qcom,pm-qos-irq-type = "affine_irq"; qcom,pm-qos-irq-latency = <67 67>; qcom,pm-qos-cpu-groups = <0x3f 0xc0>; qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>; clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, <&clock_gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface_clk", "core_clk"; /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642C 0x0 0x0 0x00010800 0x80040868>; status = "disabled"; }; qcom_seecom: qseecom@86d00000 { compatible = "qcom,qseecom"; reg = <0x86d00000 0xe00000>; reg-names = "secapp-region"; memory-region = <&qseecom_mem>; qcom,hlos-num-ce-hw-instances = <1>; qcom,hlos-ce-hw-instance = <0>; qcom,qsee-ce-hw-instance = <0>; qcom,disk-encrypt-pipe-pair = <2>; qcom,support-fde; qcom,no-clock-support; qcom,fde-key-size; qcom,appsbl-qseecom-support; qcom,commonlib64-loaded-by-uefi; qcom,qsee-reentrancy-support = <2>; }; qcom_smcinvoke: smcinvoke@86d00000 { compatible = "qcom,smcinvoke"; reg = <0x86d00000 0xe00000>; reg-names = "secapp-region"; }; qcom_rng: qrng@793000 { compatible = "qcom,msm-rng"; reg = <0x793000 0x1000>; qcom,msm-rng-iface-clk; qcom,no-qrng-config; qcom,msm-bus,name = "msm-rng-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 618 0 0>, /* No vote */ <1 618 0 300000>; /* 75 MHz */ clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; clock-names = "iface_clk"; }; ufs_ice: ufsice@1d90000 { compatible = "qcom,ice"; reg = <0x1d90000 0x8000>; qcom,enable-ice-clk; clock-names = "ufs_core_clk", "bus_clk", "iface_clk", "ice_core_clk"; clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, <&clock_gcc GCC_UFS_PHY_AHB_CLK>, <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; vdd-hba-supply = <&ufs_phy_gdsc>; qcom,msm-bus,name = "ufs_ice_noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 650 0 0>, /* No vote */ <1 650 1000 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "MAX"; qcom,instance-type = "ufs"; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xdb8>; /* PHY regs */ reg-names = "phy_mem"; #phy-cells = <0>; lanes-per-direction = <1>; clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; status = "disabled"; }; ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>; reg-names = "ufs_mem", "ufs_ice"; interrupts = <0 265 0>; phys = <&ufsphy_mem>; phy-names = "ufsphy"; lanes-per-direction = <1>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk"; clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&clock_gcc GCC_UFS_PHY_AHB_CLK>, <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; freq-table-hz = <50000000 200000000>, <0 0>, <0 0>, <37500000 150000000>, <75000000 300000000>, <0 0>, <0 0>, <0 0>; qcom,msm-bus,name = "ufshc_mem"; qcom,msm-bus,num-cases = <12>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = /* * During HS G3 UFS runs at nominal voltage corner, vote * higher bandwidth to push other buses in the data path * to run at nominal to achieve max throughput. * 4GBps pushes BIMC to run at nominal. * 200MBps pushes CNOC to run at nominal. * Vote for half of this bandwidth for HS G3 1-lane. * For max bandwidth, vote high enough to push the buses * to run in turbo voltage corner. */ <123 512 0 0>, <1 757 0 0>, /* No vote */ <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "MAX"; /* PM QoS */ qcom,pm-qos-cpu-groups = <0x3f 0xC0>; qcom,pm-qos-cpu-group-latency-us = <67 67>; qcom,pm-qos-default-cpu = <0>; pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; pinctrl-0 = <&ufs_dev_reset_assert>; pinctrl-1 = <&ufs_dev_reset_deassert>; resets = <&clock_gcc GCC_UFS_PHY_BCR>; reset-names = "core_reset"; non-removable; status = "disabled"; }; qcom_cedev: qcedev@1de0000 { compatible = "qcom,qcedev"; reg = <0x1de0000 0x20000>, <0x1dc4000 0x24000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <0 272 0>; qcom,bam-pipe-pair = <3>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,ce-hw-shared; qcom,bam-ee = <0>; qcom,msm-bus,name = "qcedev-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <125 512 0 0>, <125 512 393600 393600>; qcom,smmu-s1-enable; qcom,no-clock-support; iommus = <&apps_smmu 0x0106 0x0011>, <&apps_smmu 0x0116 0x0011>; }; qcom_msmhdcp: qcom,msm_hdcp { compatible = "qcom,msm-hdcp"; }; qcom_crypto: qcrypto@1de0000 { compatible = "qcom,qcrypto"; reg = <0x1de0000 0x20000>, <0x1dc4000 0x24000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <0 272 0>; qcom,bam-pipe-pair = <2>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,bam-ee = <0>; qcom,ce-hw-shared; qcom,clk-mgmt-sus-res; qcom,msm-bus,name = "qcrypto-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <125 512 0 0>, <125 512 393600 393600>; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; qcom,use-sw-ahash-algo; qcom,use-sw-aead-algo; qcom,use-sw-hmac-algo; qcom,smmu-s1-enable; qcom,no-clock-support; iommus = <&apps_smmu 0x0104 0x0011>, <&apps_smmu 0x0114 0x0011>; }; qcom_tzlog: tz-log@146aa720 { compatible = "qcom,tz-log"; reg = <0x146aa720 0x3000>; qcom,hyplog-enabled; hyplog-address-offset = <0x410>; hyplog-size-offset = <0x414>; }; spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>, <0xc600000 0x2000000>, <0xe600000 0x100000>, <0xe700000 0xa0000>, <0xc40a000 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <1>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <4>; cell-index = <0>; }; bluetooth: bt_wcn3990 { compatible = "qca,wcn3990"; qca,bt-vdd-core-supply = <&pm6150l_l1>; qca,bt-vdd-pa-supply = <&pm6150l_l2>; qca,bt-vdd-ldo-supply = <&pm6150l_l10>; qca,bt-vdd-core-voltage-level = <1800000 1900000>; qca,bt-vdd-pa-voltage-level = <1304000 1370000>; qca,bt-vdd-ldo-voltage-level = <3312000 3400000>; qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ }; eud: qcom,msm-eud@88e0000 { compatible = "qcom,msm-eud"; interrupt-names = "eud_irq"; interrupts = ; reg = <0x88e0000 0x2000>, <0x88e4000 0x1000>; reg-names = "eud_base", "eud_mode_mgr2"; qcom,secure-eud-en; qcom,eud-clock-vote-req; clocks = <&clock_gcc GCC_AHB2PHY_WEST_CLK>; clock-names = "eud_ahb2phy_clk"; status = "ok"; }; slim_aud: slim@62dc0000 { cell-index = <1>; compatible = "qcom,slim-ngd"; reg = <0x62dc0000 0x2c000>, <0x62d84000 0x2a000>; reg-names = "slimbus_physical", "slimbus_bam_physical"; interrupts = <0 163 0>, <0 164 0>; interrupt-names = "slimbus_irq", "slimbus_bam_irq"; qcom,apps-ch-pipes = <0x7c0000>; qcom,ea-pc = <0x2f0>; status = "disabled"; qcom,iommu-s1-bypass; iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb { compatible = "qcom,iommu-slim-ctrl-cb"; iommus = <&apps_smmu 0x17e6 0x0>, <&apps_smmu 0x17ed 0x0>, <&apps_smmu 0x17ee 0x1>, <&apps_smmu 0x17f0 0x1>; }; }; slim_qca: slim@62e40000 { cell-index = <3>; compatible = "qcom,slim-ngd"; reg = <0x62e40000 0x2c000>, <0x62e04000 0x20000>; reg-names = "slimbus_physical", "slimbus_bam_physical"; interrupts = <0 291 0>, <0 292 0>; interrupt-names = "slimbus_irq", "slimbus_bam_irq"; status = "ok"; qcom,iommu-s1-bypass; iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb { compatible = "qcom,iommu-slim-ctrl-cb"; iommus = <&apps_smmu 0x17f3 0x0>; }; /* Slimbus Slave DT for WCN3990 */ btfmslim_codec: wcn3990 { compatible = "qcom,btfmslim_slave"; elemental-addr = [00 01 20 02 17 02]; qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; }; }; tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; }; tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_block 0 0x1000>; #hwlock-cells = <1>; }; smem: qcom,smem { compatible = "qcom,smem"; memory-region = <&smem_region>; hwlocks = <&tcsr_mutex 3>; }; apcs: syscon@17c0000c { compatible = "syscon"; reg = <0x17c0000c 0x4>; }; apcs_glb: mailbox@17c00000 { compatible = "qcom,sm8150-apcs-hmss-global"; reg = <0x17c00000 0x1000>; #mbox-cells = <1>; }; qcom,msm-cdsp-loader { compatible = "qcom,cdsp-loader"; qcom,proc-img-to-load = "cdsp"; }; qcom,msm-adsprpc-mem { compatible = "qcom,msm-adsprpc-mem-region"; memory-region = <&adsp_mem>; restrict-access; }; qcom,msm_fastrpc { compatible = "qcom,msm-fastrpc-compute"; qcom,rpc-latency-us = <611>; qcom,adsp-remoteheap-vmid = <22 37>; qcom,fastrpc-adsp-audio-pdr; qcom,fastrpc-adsp-sensors-pdr; qcom,msm_fastrpc_compute_cb1 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x1081 0x0>; dma-coherent; }; qcom,msm_fastrpc_compute_cb2 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x1082 0x0>; dma-coherent; }; qcom,msm_fastrpc_compute_cb3 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x1083 0x0>; dma-coherent; }; qcom,msm_fastrpc_compute_cb4 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x1084 0x0>; dma-coherent; }; qcom,msm_fastrpc_compute_cb5 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x1085 0x0>; dma-coherent; }; qcom,msm_fastrpc_compute_cb6 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; iommus = <&apps_smmu 0x1086 0x0>; dma-coherent; }; qcom,msm_fastrpc_compute_cb9 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "cdsprpc-smd"; qcom,secure-context-bank; iommus = <&apps_smmu 0x1089 0x0>; dma-coherent; }; qcom,msm_fastrpc_compute_cb10 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "adsprpc-smd"; iommus = <&apps_smmu 0x1723 0x0>; dma-coherent; }; qcom,msm_fastrpc_compute_cb11 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "adsprpc-smd"; iommus = <&apps_smmu 0x1724 0x0>; dma-coherent; }; qcom,msm_fastrpc_compute_cb12 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "adsprpc-smd"; iommus = <&apps_smmu 0x1725 0x0>; dma-coherent; }; qcom,msm_fastrpc_compute_cb13 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "adsprpc-smd"; iommus = <&apps_smmu 0x1726 0x0>; shared-cb = <5>; dma-coherent; }; }; qcom,glink { compatible = "qcom,glink"; #address-cells = <1>; #size-cells = <1>; ranges; glink_modem: modem { qcom,remote-pid = <1>; transport = "smem"; mboxes = <&apcs_glb 12>; mbox-names = "mpss_smem"; interrupts = ; label = "modem"; qcom,glink-label = "mpss"; qcom,modem_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,msm_fastrpc_rpmsg { compatible = "qcom,msm-fastrpc-rpmsg"; qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x64 64>; }; qcom,modem_ds { qcom,glink-channels = "DS"; qcom,intents = <0x4000 0x2>; }; qcom,modem_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_adsp>, <&glink_cdsp>; }; }; glink_adsp: adsp { qcom,remote-pid = <2>; transport = "smem"; mboxes = <&apcs_glb 24>; mbox-names = "adsp_smem"; interrupts = ; label = "adsp"; qcom,glink-label = "lpass"; qcom,adsp_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,apr_tal_rpmsg { qcom,glink-channels = "apr_audio_svc"; qcom,intents = <0x200 20>; }; qcom,msm_fastrpc_rpmsg { compatible = "qcom,msm-fastrpc-rpmsg"; qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x64 64>; }; qcom,adsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_cdsp>; }; }; glink_cdsp: cdsp { qcom,remote-pid = <5>; transport = "smem"; mboxes = <&apcs_glb 4>; mbox-names = "cdsp_smem"; interrupts = ; label = "cdsp"; qcom,glink-label = "cdsp"; qcom,cdsp_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,msm_fastrpc_rpmsg { compatible = "qcom,msm-fastrpc-rpmsg"; qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x64 64>; }; qcom,msm_cdsprm_rpmsg { compatible = "qcom,msm-cdsprm-rpmsg"; qcom,glink-channels = "cdsprmglink-apps-dsp"; qcom,intents = <0x20 12>; qcom,cdsp-cdsp-l3-gov { compatible = "qcom,cdsp-l3"; qcom,target-dev = <&cdsp_cdsp_l3_lat>; }; msm_cdsp_rm: qcom,msm_cdsp_rm { compatible = "qcom,msm-cdsp-rm"; qcom,qos-latency-us = <44>; qcom,qos-maxhold-ms = <20>; #cooling-cells = <2>; }; msm_hvx_rm: qcom,msm_hvx_rm { compatible = "qcom,msm-hvx-rm"; #cooling-cells = <2>; }; }; qcom,cdsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_adsp>; }; }; glink_spi_xprt_wdsp: wdsp { qcom,remote-pid = <10>; transport = "spi"; tx-descriptors = <0x12000 0x12004>; rx-descriptors = <0x1200c 0x12010>; label = "wdsp"; qcom,glink-label = "wdsp"; qcom,wdsp_ctrl { qcom,glink-channels = "g_glink_ctrl"; qcom,intents = <0x400 1>; }; qcom,wdsp_ild { qcom,glink-channels = "g_glink_persistent_data_ild"; }; qcom,wdsp_nild { qcom,glink-channels = "g_glink_persistent_data_nild"; }; qcom,wdsp_data { qcom,glink-channels = "g_glink_audio_data"; qcom,intents = <0x1000 2>; }; qcom,diag_data { qcom,glink-channels = "DIAG_DATA"; qcom,intents = <0x4000 2>; }; qcom,diag_ctrl { qcom,glink-channels = "DIAG_CTRL"; qcom,intents = <0x4000 1>; }; qcom,diag_cmd { qcom,glink-channels = "DIAG_CMD"; qcom,intents = <0x4000 1 >; }; }; }; qcom,glinkpkt { compatible = "qcom,glinkpkt"; qcom,glinkpkt-at-mdm0 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DS"; qcom,glinkpkt-dev-name = "at_mdm0"; }; qcom,glinkpkt-apr-apps2 { qcom,glinkpkt-edge = "adsp"; qcom,glinkpkt-ch-name = "apr_apps2"; qcom,glinkpkt-dev-name = "apr_apps2"; }; qcom,glinkpkt-data40-cntl { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA40_CNTL"; qcom,glinkpkt-dev-name = "smdcntl8"; }; qcom,glinkpkt-data1 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA1"; qcom,glinkpkt-dev-name = "smd7"; }; qcom,glinkpkt-data4 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA4"; qcom,glinkpkt-dev-name = "smd8"; }; qcom,glinkpkt-data11 { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "DATA11"; qcom,glinkpkt-dev-name = "smd11"; }; }; qmp_aop: qcom,qmp-aop@c300000 { compatible = "qcom,qmp-mbox"; reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; reg-names = "msgram", "irq-reg-base"; qcom,irq-mask = <0x1>; interrupts = ; label = "aop"; qcom,early-boot; priority = <0>; mbox-desc-offset = <0x0>; #mbox-cells = <1>; }; qcom,smp2p_sleepstate { compatible = "qcom,smp2p-sleepstate"; qcom,smem-states = <&sleepstate_smp2p_out 0>; interrupt-parent = <&sleepstate_smp2p_in>; interrupts = <0 0>; interrupt-names = "smp2p-sleepstate-in"; }; qcom,smp2p-modem { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupts = ; qcom,ipc = <&apcs 0 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; modem_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; modem_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; /* ipa - inbound entry from mss */ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { qcom,entry-name = "wlan"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupts = ; qcom,ipc = <&apcs 0 26>; qcom,local-pid = <0>; qcom,remote-pid = <2>; adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; sleepstate_smp2p_out: sleepstate-out { qcom,entry-name = "sleepstate"; #qcom,smem-state-cells = <1>; }; sleepstate_smp2p_in: qcom,sleepstate-in { qcom,entry-name = "sleepstate_see"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { qcom,entry-name = "rdbg"; #qcom,smem-state-cells = <1>; }; smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { qcom,entry-name = "rdbg"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupts = ; qcom,ipc = <&apcs 0 6>; qcom,local-pid = <0>; qcom,remote-pid = <5>; cdsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; cdsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { qcom,entry-name = "rdbg"; #qcom,smem-state-cells = <1>; }; smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { qcom,entry-name = "rdbg"; interrupt-controller; #interrupt-cells = <2>; }; }; thermal_zones: thermal-zones {}; tsens0: tsens@c222000 { compatible = "qcom,sm6150-tsens"; reg = <0xc222000 0x8>, <0xc263000 0x1ff>; reg-names = "tsens_srot_physical", "tsens_tm_physical"; interrupts = <0 506 0>, <0 508 0>; interrupt-names = "tsens-upper-lower", "tsens-critical"; tsens-reinit-wa; #thermal-sensor-cells = <1>; }; qcom,lpass@62400000 { compatible = "qcom,pil-tz-generic"; reg = <0x62400000 0x00100>; vdd_cx-supply = <&L8A_LEVEL>; qcom,vdd_cx-uV-uA = ; qcom,proxy-reg-names = "vdd_cx"; clocks = <&clock_rpmh RPMH_CXO_CLK>; clock-names = "xo"; qcom,proxy-clock-names = "xo"; qcom,pas-id = <1>; qcom,proxy-timeout-ms = <10000>; qcom,smem-id = <423>; qcom,sysmon-id = <1>; qcom,ssctl-instance-id = <0x14>; qcom,firmware-name = "adsp"; memory-region = <&pil_adsp_mem>; qcom,signal-aop; qcom,complete-ramdump; /* Inputs from lpass */ interrupts-extended = <&pdc 0 162 1>, <&adsp_smp2p_in 0 0>, <&adsp_smp2p_in 2 0>, <&adsp_smp2p_in 1 0>, <&adsp_smp2p_in 3 0>, <&adsp_smp2p_in 7 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", "qcom,stop-ack", "qcom,shutdown-ack"; /* Outputs to lpass */ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "qcom,force-stop"; mboxes = <&qmp_aop 0>; mbox-names = "adsp-pil"; }; pil_modem: qcom,mss@4080000 { compatible = "qcom,pil-tz-generic"; reg = <0x4080000 0x100>; clocks = <&clock_rpmh RPMH_CXO_CLK>; clock-names = "xo"; qcom,proxy-clock-names = "xo"; vdd_cx-supply = <&VDD_CX_LEVEL>; qcom,vdd_cx-uV-uA = ; vdd_mss-supply = <&VDD_MSS_LEVEL>; qcom,vdd_mss-uV-uA = ; qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; qcom,firmware-name = "modem"; memory-region = <&pil_modem_mem>; qcom,proxy-timeout-ms = <10000>; qcom,sysmon-id = <0>; qcom,ssctl-instance-id = <0x12>; qcom,pas-id = <4>; qcom,smem-id = <421>; qcom,signal-aop; qcom,minidump-id = <3>; qcom,aux-minidump-ids = <4>; qcom,complete-ramdump; /* Inputs from mss */ interrupts-extended = <&pdc 0 266 1>, <&modem_smp2p_in 0 0>, <&modem_smp2p_in 2 0>, <&modem_smp2p_in 1 0>, <&modem_smp2p_in 3 0>, <&modem_smp2p_in 7 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", "qcom,stop-ack", "qcom,shutdown-ack"; /* Outputs to mss */ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "qcom,force-stop"; mboxes = <&qmp_aop 0>; mbox-names = "mss-pil"; }; qcom,turing@8300000 { compatible = "qcom,pil-tz-generic"; reg = <0x8300000 0x100000>; vdd_cx-supply = <&VDD_CX_LEVEL>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = ; clocks = <&clock_rpmh RPMH_CXO_CLK>; clock-names = "xo"; qcom,proxy-clock-names = "xo"; qcom,pas-id = <18>; qcom,proxy-timeout-ms = <10000>; qcom,smem-id = <601>; qcom,sysmon-id = <7>; qcom,ssctl-instance-id = <0x17>; qcom,firmware-name = "cdsp"; memory-region = <&pil_cdsp_mem>; qcom,signal-aop; qcom,complete-ramdump; /* Inputs from turing */ interrupts-extended = <&pdc 0 578 1>, <&cdsp_smp2p_in 0 0>, <&cdsp_smp2p_in 2 0>, <&cdsp_smp2p_in 1 0>, <&cdsp_smp2p_in 3 0>, <&cdsp_smp2p_in 7 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", "qcom,stop-ack", "qcom,shutdown-ack"; /* Outputs to turing */ qcom,smem-states = <&cdsp_smp2p_out 0>; qcom,smem-state-names = "qcom,force-stop"; mboxes = <&qmp_aop 0>; mbox-names = "cdsp-pil"; }; qcom,venus@aae0000 { compatible = "qcom,pil-tz-generic"; reg = <0xaae0000 0x4000>; vdd-supply = <&venus_gdsc>; qcom,proxy-reg-names = "vdd"; clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>, <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; clock-names = "core_clk", "iface_clk", "bus_clk"; qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk"; qcom,pas-id = <9>; qcom,msm-bus,name = "pil-venus"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <63 512 0 0>, <63 512 0 304000>; qcom,proxy-timeout-ms = <100>; qcom,firmware-name = "venus"; memory-region = <&pil_video_mem>; }; qcom,msm_gsi { compatible = "qcom,msm_gsi"; }; qcom,rmnet-ipa { compatible = "qcom,rmnet-ipa3"; qcom,rmnet-ipa-ssr; qcom,ipa-platform-type-msm; qcom,ipa-advertise-sg-support; qcom,ipa-napi-enable; }; ipa_hw: qcom,ipa@1e00000 { compatible = "qcom,ipa"; reg = <0x1e00000 0x34000>, <0x1e04000 0x2c000>; reg-names = "ipa-base", "gsi-base"; interrupts = <0 311 0>, <0 432 0>; interrupt-names = "ipa-irq", "gsi-irq"; qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */ qcom,ipa-hw-mode = <0>; qcom,ee = <0>; qcom,use-ipa-tethering-bridge; qcom,modem-cfg-emb-pipe-flt; qcom,ipa-wdi2; qcom,ipa-wdi2_over_gsi; qcom,ipa-fltrt-not-hashable; qcom,use-64-bit-dma-mask; qcom,arm-smmu; qcom,smmu-fast-map; qcom,use-ipa-pm; qcom,bandwidth-vote-for-ipa; qcom,ipa-endp-delay-wa; qcom,msm-bus,name = "ipa"; qcom,msm-bus,num-cases = <5>; qcom,msm-bus,num-paths = <4>; qcom,msm-bus,vectors-KBps = /* No vote */ , , , , /* SVS2 */ , , , , /* SVS */ , , , , /* NOMINAL */ , , , , /* TURBO */ , , , ; qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; qcom,throughput-threshold = <310 600 1000>; qcom,scaling-exceptions = <>; /* smp2p information */ qcom,smp2p_map_ipa_1_out { compatible = "qcom,smp2p-map-ipa-1-out"; qcom,smem-states = <&smp2p_ipa_1_out 0>; qcom,smem-state-names = "ipa-smp2p-out"; }; qcom,smp2p_map_ipa_1_in { compatible = "qcom,smp2p-map-ipa-1-in"; interrupts-extended = <&smp2p_ipa_1_in 0 0>; interrupt-names = "ipa-smp2p-in"; }; }; ipa_smmu_ap: ipa_smmu_ap { compatible = "qcom,ipa-smmu-ap-cb"; qcom,smmu-s1-bypass; iommus = <&apps_smmu 0x1520 0x0>; qcom,iova-mapping = <0x20000000 0x40000000>; /* modem tables in IMEM */ qcom,additional-mapping = <0x146A8000 0x146A8000 0x2000>; }; ipa_smmu_wlan: ipa_smmu_wlan { compatible = "qcom,ipa-smmu-wlan-cb"; qcom,smmu-s1-bypass; iommus = <&apps_smmu 0x1521 0x0>; /* ipa-uc ram */ qcom,additional-mapping = <0x1e60000 0x1e60000 0x80000>; }; ipa_smmu_uc: ipa_smmu_uc { compatible = "qcom,ipa-smmu-uc-cb"; qcom,smmu-s1-bypass; iommus = <&apps_smmu 0x1522 0x0>; qcom,iova-mapping = <0x40400000 0x1fc00000>; }; qcom,ipa_fws { compatible = "qcom,pil-tz-generic"; qcom,pas-id = <0xf>; qcom,firmware-name = "ipa_fws"; qcom,pil-force-shutdown; memory-region = <&pil_ipa_fw_mem>; }; icnss: qcom,icnss@18800000 { compatible = "qcom,icnss"; reg = <0x18800000 0x800000>, <0xa0000000 0x10000000>, <0xb0000000 0x10000>; reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; iommus = <&apps_smmu 0x1640 0x1>; interrupts = <0 414 0 /* CE0 */ >, <0 415 0 /* CE1 */ >, <0 416 0 /* CE2 */ >, <0 417 0 /* CE3 */ >, <0 418 0 /* CE4 */ >, <0 419 0 /* CE5 */ >, <0 420 0 /* CE6 */ >, <0 421 0 /* CE7 */ >, <0 422 0 /* CE8 */ >, <0 423 0 /* CE9 */ >, <0 424 0 /* CE10 */ >, <0 425 0 /* CE11 */ >; qcom,smmu-s1-bypass; qcom,wlan-msa-memory = <0x100000>; qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; vdd-cx-mx-supply = <&pm6150_l9>; vdd-1.8-xo-supply = <&pm6150l_l1>; vdd-1.3-rfa-supply = <&pm6150l_l2>; vdd-3.3-ch0-supply = <&pm6150l_l10>; qcom,vdd-cx-mx-config = <640000 640000>; qcom,smp2p_map_wlan_1_in { interrupts-extended = <&smp2p_wlan_1_in 0 0>, <&smp2p_wlan_1_in 1 0>; interrupt-names = "qcom,smp2p-force-fatal-error", "qcom,smp2p-early-crash-ind"; }; }; qcom,rmtfs_sharedmem@0 { compatible = "qcom,sharedmem-uio"; reg = <0x0 0x200000>; reg-names = "rmtfs"; qcom,client-id = <0x00000001>; qcom,guard-memory; }; llcc_pmu: llcc-pmu@90cc000 { compatible = "qcom,qcom-llcc-pmu"; reg = <0x090cc000 0x300>; reg-names = "lagg-base"; }; llcc_bw_opp_table: llcc-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ }; cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; operating-points-v2 = <&llcc_bw_opp_table>; }; cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 { compatible = "qcom,bimc-bwmon4"; reg = <0x90b6300 0x300>, <0x90b6200 0x200>; reg-names = "base", "global_base"; interrupts = ; qcom,mport = <0>; qcom,hw-timer-hz = <19200000>; qcom,target-dev = <&cpu_cpu_llcc_bw>; qcom,count-unit = <0x10000>; }; ddr_bw_opp_table: ddr-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ }; cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; operating-points-v2 = <&ddr_bw_opp_table>; }; cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 { compatible = "qcom,bimc-bwmon5"; reg = <0x90cd000 0x1000>; reg-names = "base"; interrupts = ; qcom,hw-timer-hz = <19200000>; qcom,target-dev = <&cpu_llcc_ddr_bw>; qcom,count-unit = <0x10000>; }; suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 0, 4); /* 0 MB/s */ BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ }; cdsp_cdsp_l3_lat: qcom,cdsp-cdsp-l3-lat { compatible = "devfreq-simple-dev"; clock-names = "devfreq_clk"; clocks = <&clock_cpucc L3_MISC_VOTE_CLK>; governor = "powersave"; }; cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { compatible = "devfreq-simple-dev"; clock-names = "devfreq_clk"; clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>; governor = "performance"; }; cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; qcom,target-dev = <&cpu0_cpu_l3_lat>; qcom,cachemiss-ev = <0x17>; qcom,stall-cycle-ev = <0xE7>; qcom,core-dev-table = < 576000 300000000 >, < 1017600 556800000 >, < 1209660 806400000 >, < 1516800 940800000 >, < 1804800 1363200000 >; }; cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { compatible = "devfreq-simple-dev"; clock-names = "devfreq_clk"; clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>; governor = "performance"; }; cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU6 &CPU7>; qcom,target-dev = <&cpu6_cpu_l3_lat>; qcom,cachemiss-ev = <0x17>; qcom,stall-cycle-ev = <0x15E>; qcom,core-dev-table = < 1017600 556800000 >, < 1209600 806400000 >, < 1516800 940800000 >, < 1708800 1209600000 >, < 2208000 1363200000 >; }; cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; operating-points-v2 = <&llcc_bw_opp_table>; }; cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; qcom,target-dev = <&cpu0_cpu_llcc_lat>; qcom,cachemiss-ev = <0x2A>; qcom,stall-cycle-ev = <0xE7>; qcom,core-dev-table = < 748000 MHZ_TO_MBPS(150, 16) >, < 1209600 MHZ_TO_MBPS(300, 16) >, < 1516800 MHZ_TO_MBPS(466, 16) >, < 1804800 MHZ_TO_MBPS(600, 16) >; }; cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; operating-points-v2 = <&llcc_bw_opp_table>; }; cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU6 &CPU7>; qcom,target-dev = <&cpu6_cpu_llcc_lat>; qcom,cachemiss-ev = <0x2A>; qcom,stall-cycle-ev = <0x15E>; qcom,core-dev-table = < 768000 MHZ_TO_MBPS(300, 16) >, < 1017600 MHZ_TO_MBPS(466, 16) >, < 1209600 MHZ_TO_MBPS(600, 16) >, < 1708800 MHZ_TO_MBPS(806, 16) >, < 2208000 MHZ_TO_MBPS(933, 16) >; }; cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; operating-points-v2 = <&ddr_bw_opp_table>; }; cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; qcom,target-dev = <&cpu0_llcc_ddr_lat>; qcom,cachemiss-ev = <0x1000>; qcom,stall-cycle-ev = <0xE7>; qcom,core-dev-table = < 748000 MHZ_TO_MBPS( 300, 4) >, < 1017600 MHZ_TO_MBPS( 451, 4) >, < 1209600 MHZ_TO_MBPS( 547, 4) >, < 1516800 MHZ_TO_MBPS( 768, 4) >, < 1804800 MHZ_TO_MBPS(1017, 4) >; }; cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; operating-points-v2 = <&ddr_bw_opp_table>; }; cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU6 &CPU7>; qcom,target-dev = <&cpu6_llcc_ddr_lat>; qcom,cachemiss-ev = <0x1000>; qcom,stall-cycle-ev = <0x15E>; qcom,core-dev-table = < 768000 MHZ_TO_MBPS( 451, 4) >, < 1017600 MHZ_TO_MBPS( 547, 4) >, < 1209600 MHZ_TO_MBPS(1017, 4) >, < 1708800 MHZ_TO_MBPS(1555, 4) >, < 2208000 MHZ_TO_MBPS(1804, 4) >; }; cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; operating-points-v2 = <&ddr_bw_opp_table>; }; cpu0_computemon: qcom,cpu0-computemon { compatible = "qcom,arm-cpu-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; qcom,core-dev-table = < 748800 MHZ_TO_MBPS( 300, 4) >, < 1209600 MHZ_TO_MBPS( 451, 4) >, < 1593600 MHZ_TO_MBPS( 547, 4) >, < 1804800 MHZ_TO_MBPS( 768, 4) >; }; cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; operating-points-v2 = <&ddr_bw_opp_table>; }; cpu6_computemon: qcom,cpu6-computemon { compatible = "qcom,arm-cpu-mon"; qcom,cpulist = <&CPU6 &CPU7>; qcom,target-dev = <&cpu6_cpu_ddr_latfloor>; qcom,core-dev-table = < 1017600 MHZ_TO_MBPS( 300, 4) >, < 1209600 MHZ_TO_MBPS( 547, 4) >, < 1516800 MHZ_TO_MBPS( 768, 4) >, < 1708800 MHZ_TO_MBPS(1017, 4) >, < 2208000 MHZ_TO_MBPS(1804, 4) >; }; bus_proxy_client: qcom,bus_proxy_client { compatible = "qcom,bus-proxy-client"; qcom,msm-bus,name = "bus-proxy-client"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = , ; qcom,msm-bus,active-only; status = "ok"; }; keepalive_opp_table: keepalive-opp-table { compatible = "operating-points-v2"; opp-1 { opp-hz = /bits/ 64 < 1 >; }; }; snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive { compatible = "qcom,devbw"; governor = "powersave"; qcom,src-dst-ports = <1 627>; qcom,active-only; status = "ok"; operating-points-v2 = <&keepalive_opp_table>; }; cx_ipeak_lm: cx_ipeak@01fed000 { compatible = "qcom,cx-ipeak-v1"; reg = <0x1fed000 0x28>; }; demux { compatible = "qcom,demux"; }; }; #include "pm6150.dtsi" #include "pm6150l.dtsi" #include "sm6150-pinctrl.dtsi" #include "sm6150-slpi-pinctrl.dtsi" #include "sm6150-regulator.dtsi" #include "sm6150-pm.dtsi" #include "sm6150-gdsc.dtsi" #include "sm6150-qupv3.dtsi" #include "sm6150-thermal.dtsi" #include "sm6150-gpu.dtsi" #include "sm6150-usb.dtsi" &usb0 { extcon = <&pm6150_pdphy>, <&pm6150_charger>, <&eud>; }; &pm6150_vadc { sdm_therm { reg = ; label = "sdm_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; smb1390_therm { reg = ; label = "smb1390_therm"; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; conn_therm { reg = ; label = "conn_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; }; &pm6150_adc_tm { io-channels = <&pm6150_vadc ADC_XO_THERM_PU2>, <&pm6150_vadc ADC_AMUX_THM2_PU2>, <&pm6150_vadc ADC_AMUX_THM4_PU2>; /* Channel nodes */ xo_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; sdm_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; conn_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; }; &pm6150l_vadc { emmc_ufs_therm { reg = ; label = "emmc_ufs_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; rf_pa0_therm { reg = ; label = "rf_pa0_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; rf_pa1_therm { reg = ; label = "rf_pa1_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; camera_flash_therm { reg = ; label = "camera_flash_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; }; }; &pm6150l_adc_tm { io-channels = <&pm6150l_vadc ADC_AMUX_THM1_PU2>, <&pm6150l_vadc ADC_AMUX_THM2_PU2>, <&pm6150l_vadc ADC_GPIO1_PU2>; /* Channel nodes */ emmc_ufs_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; rf_pa0_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; camera_flash_therm { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; }; &emac_gdsc { status = "ok"; }; &pcie_0_gdsc { status = "ok"; }; &ufs_phy_gdsc { status = "ok"; }; &usb30_prim_gdsc { status = "ok"; }; &usb20_sec_gdsc { status = "ok"; }; &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { status = "ok"; }; &hlos1_vote_aggre_noc_mmu_tbu1_gdsc { status = "ok"; }; &hlos1_vote_aggre_noc_mmu_tbu2_gdsc { status = "ok"; }; &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { status = "ok"; }; &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { status = "ok"; }; &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { status = "ok"; }; &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { status = "ok"; }; &bps_gdsc { qcom,support-hw-trigger; status = "ok"; }; &ife_0_gdsc { status = "ok"; }; &ife_1_gdsc { status = "ok"; }; &ipe_0_gdsc { qcom,support-hw-trigger; status = "ok"; }; &titan_top_gdsc { status = "ok"; }; &mdss_core_gdsc { status = "ok"; }; &gpu_cx_gdsc { parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gpu_gx_gdsc { clock-names = "core_root_clk"; clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK_SRC>; qcom,force-enable-root-clk; parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &vcodec0_gdsc { qcom,support-hw-trigger; status = "ok"; }; &venus_gdsc { status = "ok"; }; &qupv3_se3_i2c { status = "ok"; fsa4480: fsa4480@43 { compatible = "qcom,fsa4480-i2c"; reg = <0x43>; pinctrl-names = "default"; pinctrl-0 = <&fsa_usbc_ana_en>; }; }; #include "sm6150-camera.dtsi" #include "sm6150-ion.dtsi" #include "msm-arm-smmu-sm6150.dtsi" #include "sm6150-coresight.dtsi" #include "sm6150-bus.dtsi" #include "sm6150-vidc.dtsi" #include "sm6150-audio.dtsi" #include "sm6150-sde-pll.dtsi" #include "sm6150-sde.dtsi" #include "msm-rdbg.dtsi" &msm_vidc { qcom,cx-ipeak-data = <&cx_ipeak_lm 4>; qcom,clock-freq-threshold = <460000000>; }; &msm_audio_ion { qcom,iova-start-addr = <0x20000000>; };