/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/msm/msm-bus-ids.h>

&soc {
	/* QUPv3 West Instances
	 * West 0 : SE 0
	 * West 1 : SE 1
	 * West 2 : SE 2
	 * West 3 : SE 3
	 * West 4 : SE 4
	 * West 5 : SE 5
	 * West 6 : SE 6
	 * West 7 : SE 7
	 */
	qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x8c0000 0x6000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_0>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
		qcom,iommu-s1-bypass;
		status = "ok";

		iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {
			compatible = "qcom,qupv3-geni-se-cb";
			iommus = <&apps_smmu 0x4c3 0x0>;
		};
	};

	/* I2C */
	qupv3_se0_i2c: i2c@880000 {
		compatible = "qcom,i2c-geni";
		reg = <0x880000 0x4000>;
		interrupts = <GIC_SPI 601 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se0_i2c_active>;
		pinctrl-1 = <&qupv3_se0_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se1_i2c: i2c@884000 {
		compatible = "qcom,i2c-geni";
		reg = <0x884000 0x4000>;
		interrupts = <GIC_SPI 602 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se1_i2c_active>;
		pinctrl-1 = <&qupv3_se1_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se2_i2c: i2c@888000 {
		compatible = "qcom,i2c-geni";
		reg = <0x888000 0x4000>;
		interrupts = <GIC_SPI 603 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_i2c_active>;
		pinctrl-1 = <&qupv3_se2_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se3_i2c: i2c@88c000 {
		compatible = "qcom,i2c-geni";
		reg = <0x88c000 0x4000>;
		interrupts = <GIC_SPI 604 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se3_i2c_active>;
		pinctrl-1 = <&qupv3_se3_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se4_i2c: i2c@890000 {
		compatible = "qcom,i2c-geni";
		reg = <0x890000 0x4000>;
		interrupts = <GIC_SPI 605 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se4_i2c_active>;
		pinctrl-1 = <&qupv3_se4_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se5_i2c: i2c@894000 {
		compatible = "qcom,i2c-geni";
		reg = <0x894000 0x4000>;
		interrupts = <GIC_SPI 606 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se5_i2c_active>;
		pinctrl-1 = <&qupv3_se5_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se6_i2c: i2c@898000 {
		compatible = "qcom,i2c-geni";
		reg = <0x898000 0x4000>;
		interrupts = <GIC_SPI 607 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_i2c_active>;
		pinctrl-1 = <&qupv3_se6_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se7_i2c: i2c@89c000 {
		compatible = "qcom,i2c-geni";
		reg = <0x89c000 0x4000>;
		interrupts = <GIC_SPI 608 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se7_i2c_active>;
		pinctrl-1 = <&qupv3_se7_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	/* SPI */
	qupv3_se0_spi: spi@880000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x880000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se0_spi_active>;
		pinctrl-1 = <&qupv3_se0_spi_sleep>;
		interrupts = <GIC_SPI 601 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se1_spi: spi@884000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x884000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se1_spi_active>;
		pinctrl-1 = <&qupv3_se1_spi_sleep>;
		interrupts = <GIC_SPI 602 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se2_spi: spi@888000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x888000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_spi_active>;
		pinctrl-1 = <&qupv3_se2_spi_sleep>;
		interrupts = <GIC_SPI 603 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se3_spi: spi@88c000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x88c000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se3_spi_active>;
		pinctrl-1 = <&qupv3_se3_spi_sleep>;
		interrupts = <GIC_SPI 604 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se4_spi: spi@890000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x890000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se4_spi_active>;
		pinctrl-1 = <&qupv3_se4_spi_sleep>;
		interrupts = <GIC_SPI 605 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se5_spi: spi@894000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x894000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se5_spi_active>;
		pinctrl-1 = <&qupv3_se5_spi_sleep>;
		interrupts = <GIC_SPI 606 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se6_spi: spi@898000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x898000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_spi_active>;
		pinctrl-1 = <&qupv3_se6_spi_sleep>;
		interrupts = <GIC_SPI 607 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se7_spi: spi@89c000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x89c000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se7_spi_active>;
		pinctrl-1 = <&qupv3_se7_spi_sleep>;
		interrupts = <GIC_SPI 608 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	/* 4-wire UART */
	qupv3_se4_4uart: qcom,qup_uart@890000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0x890000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "active", "sleep";
		pinctrl-0 = <&qupv3_se4_default_ctsrtsrx>,
				<&qupv3_se4_default_tx>;
		pinctrl-1 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>,
						<&qupv3_se4_tx>;
		pinctrl-2 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>,
						<&qupv3_se4_tx>;
		interrupts-extended = <&pdc GIC_SPI 605 0>,
				<&tlmm 54 0>;
		qcom,wrapper-core = <&qupv3_0>;
		qcom,wakeup-byte = <0xFD>;
		status = "disabled";
	};

	/* QUPv3 East0 and East1 Instances
	 * East1 0 : SE 8
	 * East1 1 : SE 9
	 * East1 2 : SE 10
	 * East1 3 : SE 11
	 * East1 4 : SE 12
	 * East1 5 : SE 16
	 * East1 0 : SE 17
	 * East0 1 : SE 18
	 * East0 2 : SE 19
	 * East0 3 : SE 13
	 * East0 4 : SE 14
	 * East0 5 : SE 15
	 */

	/* QUPv3 East1 Instances */
	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0xac0000 0x6000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
		qcom,iommu-s1-bypass;
		status = "ok";

		iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {
			compatible = "qcom,qupv3-geni-se-cb";
			iommus = <&apps_smmu 0x603 0x0>;
		};
	};

	/* 2-wire UART */

	/* Debug UART Instance for CDP/MTP platform */
	qupv3_se12_2uart: qcom,qup_uart@a90000 {
		compatible = "qcom,msm-geni-console";
		reg = <0xa90000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se12_2uart_active>;
		pinctrl-1 = <&qupv3_se12_2uart_sleep>;
		interrupts = <GIC_SPI 357 0>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	/* Debug UART Instance for RUMI platform */
	qupv3_se10_2uart: qcom,qup_uart@a88000 {
		compatible = "qcom,msm-geni-console";
		reg = <0xa88000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se10_2uart_active>;
		pinctrl-1 = <&qupv3_se10_2uart_sleep>;
		interrupts = <GIC_SPI 355 0>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	/* I2C */
	qupv3_se8_i2c: i2c@a80000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa80000 0x4000>;
		interrupts = <GIC_SPI 353 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se8_i2c_active>;
		pinctrl-1 = <&qupv3_se8_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se9_i2c: i2c@a84000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa84000 0x4000>;
		interrupts = <GIC_SPI 354 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se9_i2c_active>;
		pinctrl-1 = <&qupv3_se9_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se10_i2c: i2c@a88000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa88000 0x4000>;
		interrupts = <GIC_SPI 355 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se10_i2c_active>;
		pinctrl-1 = <&qupv3_se10_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se11_i2c: i2c@a8c000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa8c000 0x4000>;
		interrupts = <GIC_SPI 356 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se11_i2c_active>;
		pinctrl-1 = <&qupv3_se11_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se12_i2c: i2c@a90000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa90000 0x4000>;
		interrupts = <GIC_SPI 357 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se12_i2c_active>;
		pinctrl-1 = <&qupv3_se12_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se13_i2c: i2c@c8c000 {
		compatible = "qcom,i2c-geni";
		reg = <0xc8c000 0x4000>;
		interrupts = <GIC_SPI 585 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se13_i2c_active>;
		pinctrl-1 = <&qupv3_se13_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	/* SPI */
	qupv3_se8_spi: spi@a80000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xa80000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se8_spi_active>;
		pinctrl-1 = <&qupv3_se8_spi_active>;
		interrupts = <GIC_SPI 353 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se9_spi: spi@a84000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xa84000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se9_spi_active>;
		pinctrl-1 = <&qupv3_se9_spi_sleep>;
		interrupts = <GIC_SPI 354 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se10_spi: spi@a88000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xa88000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se10_spi_active>;
		pinctrl-1 = <&qupv3_se10_spi_sleep>;
		interrupts = <GIC_SPI 355 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se11_spi: spi@a8c000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xa8c000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se11_spi_active>;
		pinctrl-1 = <&qupv3_se11_spi_sleep>;
		interrupts = <GIC_SPI 356 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se12_spi: spi@a90000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xa90000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se12_spi_active>;
		pinctrl-1 = <&qupv3_se12_spi_sleep>;
		interrupts = <GIC_SPI 357 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se13_spi: spi@c8c000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc8c000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se13_spi_active>;
		pinctrl-1 = <&qupv3_se13_spi_sleep>;
		interrupts = <GIC_SPI 585 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	/* QUPv3 East0 Instances */
	qupv3_2: qcom,qupv3_2_geni_se@cc0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0xcc0000 0x6000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_2>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
		qcom,iommu-s1-bypass;
		status = "ok";

		iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb {
			compatible = "qcom,qupv3-geni-se-cb";
			iommus = <&apps_smmu 0x7a3 0x0>;
		};
	};

	/* 4-wire UART */
	qupv3_se13_4uart: qcom,qup_uart@c8c000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0xc8c000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "active", "sleep";
		pinctrl-0 = <&qupv3_se13_default_ctsrtsrx>,
				<&qupv3_se13_default_tx>;
		pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,
						<&qupv3_se13_tx>;
		pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,
						<&qupv3_se13_tx>;
		interrupts-extended = <&pdc GIC_SPI 585 0>,
				<&tlmm 46 0>;
		qcom,wrapper-core = <&qupv3_2>;
		qcom,wakeup-byte = <0xFD>;
		status = "disabled";
	};

	/* I2C */
	qupv3_se14_i2c: i2c@0xc90000 {
		compatible = "qcom,i2c-geni";
		reg = <0xc90000 0x4000>;
		interrupts = <GIC_SPI 586 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se14_i2c_active>;
		pinctrl-1 = <&qupv3_se14_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se15_i2c: i2c@0xc94000 {
		compatible = "qcom,i2c-geni";
		reg = <0xc94000 0x4000>;
		interrupts = <GIC_SPI 587 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se15_i2c_active>;
		pinctrl-1 = <&qupv3_se15_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se16_i2c: i2c@0xa94000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa94000 0x4000>;
		interrupts = <GIC_SPI 358 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se16_i2c_active>;
		pinctrl-1 = <&qupv3_se16_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se17_i2c: i2c@0xc80000 {
		compatible = "qcom,i2c-geni";
		reg = <0xc80000 0x4000>;
		interrupts = <GIC_SPI 373 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se17_i2c_active>;
		pinctrl-1 = <&qupv3_se17_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se18_i2c: i2c@0xc84000 {
		compatible = "qcom,i2c-geni";
		reg = <0xc84000 0x4000>;
		interrupts = <GIC_SPI 583 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se18_i2c_active>;
		pinctrl-1 = <&qupv3_se18_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se19_i2c: i2c@0xc88000 {
		compatible = "qcom,i2c-geni";
		reg = <0xc88000 0x4000>;
		interrupts = <GIC_SPI 584 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se19_i2c_active>;
		pinctrl-1 = <&qupv3_se19_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	/* SPI */
	qupv3_se14_spi: spi@c90000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc90000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se14_spi_active>;
		pinctrl-1 = <&qupv3_se14_spi_sleep>;
		interrupts = <GIC_SPI 586 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se15_spi: spi@c94000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc94000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se15_spi_active>;
		pinctrl-1 = <&qupv3_se15_spi_sleep>;
		interrupts = <GIC_SPI 587 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se16_spi: spi@a94000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xa94000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se16_spi_active>;
		pinctrl-1 = <&qupv3_se16_spi_sleep>;
		interrupts = <GIC_SPI 358 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se17_spi: spi@c80000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc80000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se17_spi_active>;
		pinctrl-1 = <&qupv3_se17_spi_sleep>;
		interrupts = <GIC_SPI 373 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se18_spi: spi@c84000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc84000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se18_spi_active>;
		pinctrl-1 = <&qupv3_se18_spi_sleep>;
		interrupts = <GIC_SPI 583 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se19_spi: spi@c88000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xc88000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se19_spi_active>;
		pinctrl-1 = <&qupv3_se19_spi_sleep>;
		interrupts = <GIC_SPI 584 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	 /* QUPv3 SSC Instances */
	qupv3_3: qcom,qupv3_3_geni_se@26c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x26c0000 0x6000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_SENSORS_AHB>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
		qcom,iommu-s1-bypass;
		qcom,subsys-name = "slpi";
		clock-names = "corex", "core2x";
		clocks = <&clock_scc SCC_QUPV3_CORE_CLK>,
			<&clock_scc SCC_QUPV3_2XCORE_CLK>;
		status = "disabled";

		iommu_qupv3_3_geni_se_cb: qcom,iommu_qupv3_3_geni_se_cb {
			compatible = "qcom,qupv3-geni-se-cb";
			iommus = <&apps_smmu 0x4e3 0x0>;
		};
	};

	/* I2C */
	qupv3_se20_i2c: i2c@2680000 {
		compatible = "qcom,i2c-geni";
		reg = <0x2680000 0x4000>;
		interrupts = <GIC_SPI 442 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE0_CLK>,
			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se20_i2c_active>;
		pinctrl-1 = <&qupv3_se20_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_3>;
		status = "disabled";
	};

	qupv3_se21_i2c: i2c@2684000 {
		compatible = "qcom,i2c-geni";
		reg = <0x2684000 0x4000>;
		interrupts = <GIC_SPI 443 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE1_CLK>,
			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se21_i2c_active>;
		pinctrl-1 = <&qupv3_se21_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_3>;
		status = "disabled";
	};

	qupv3_se22_i2c: i2c@2688000 {
		compatible = "qcom,i2c-geni";
		reg = <0x2688000 0x4000>;
		interrupts = <GIC_SPI 444 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE2_CLK>,
			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se22_i2c_active>;
		pinctrl-1 = <&qupv3_se22_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_3>;
		status = "disabled";
	};

	qupv3_se23_i2c: i2c@268c000 {
		compatible = "qcom,i2c-geni";
		reg = <0x268c000 0x4000>;
		interrupts = <GIC_SPI 445 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE3_CLK>,
			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se23_i2c_active>;
		pinctrl-1 = <&qupv3_se23_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_3>;
		status = "disabled";
	};

	/* SPI */
	qupv3_se21_spi: spi@2684000 {
		compatible = "qcom,spi-geni";
		reg = <0x2684000 0x4000>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 443 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE1_CLK>,
			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se21_spi_active>;
		pinctrl-1 = <&qupv3_se21_spi_sleep>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_3>;
		status = "disabled";
	};

	qupv3_se22_spi: spi@2688000 {
		compatible = "qcom,spi-geni";
		reg = <0x2688000 0x4000>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 444 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_scc SCC_QUPV3_SE2_CLK>,
			<&clock_scc SCC_QUPV3_M_HCLK_CLK>,
			<&clock_scc SCC_QUPV3_S_HCLK_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se22_spi_active>;
		pinctrl-1 = <&qupv3_se22_spi_sleep>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_3>;
		qcom,disable-dma;
		status = "disabled";
	};
};