/*
 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include "qcs405-pinctrl.dtsi"

/ {
	aliases {
		spi1 = &spi_1;
		spi2 = &spi_2;
		spi3 = &spi_3;
		spi4 = &spi_4;
		spi5 = &spi_5;
		spi6 = &spi_6;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &i2c_4;
		i2c5 = &i2c_5;
		i2c6 = &i2c_6;
	};
};


&soc {

	dma_blsp1: qcom,sps-dma@7884000{ /* BLSP1 */
		#dma-cells = <4>;
		compatible = "qcom,sps-dma";
		reg = <0x7884000 0x25000>;
		interrupts = <0 238 0>;
		qcom,summing-threshold = <0x10>;
	};

	dma_blsp2: qcom,sps-dma@7ac4000{ /* BLSP2 */
		#dma-cells = <4>;
		compatible = "qcom,sps-dma";
		reg = <0x7ac4000 0x17000>;
		interrupts = <0 239 0>;
		qcom,summing-threshold = <0x10>;
	};

	i2c_1: i2c@78b5000 { /* BLSP1 QUP1 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x78b5000 0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 95 0>;
		dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
			<&dma_blsp1 9 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in  = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
			 <&clock_gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_1_active>;
		pinctrl-1 = <&i2c_1_sleep>;
		status = "disabled";
	};

	i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x78b6000  0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 96 0>;
		dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
			<&dma_blsp1 11 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in  = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
			 <&clock_gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_2_active>;
		pinctrl-1 = <&i2c_2_sleep>;
		status = "disabled";
	};

	i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x78b7000  0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 97 0>;
		dmas = <&dma_blsp1 12 64 0x20000020 0x20>,
			<&dma_blsp1 13 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in  = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
			 <&clock_gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_3_sda_active>, <&i2c_3_scl_active>;
		pinctrl-1 = <&i2c_3_sleep>;
		status = "disabled";
	};

	i2c_4: i2c@78b8000 { /* BLSP1 QUP4 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x78b8000  0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 98 0>;
		dmas = <&dma_blsp1 14 64 0x20000020 0x20>,
			<&dma_blsp1 15 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in  = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
			 <&clock_gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_4_active>;
		pinctrl-1 = <&i2c_4_sleep>;
		status = "disabled";
	};

	i2c_5: i2c@78b9000 { /* BLSP2 QUP1 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x78b9000  0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 99 0>;
		dmas = <&dma_blsp1 16 64 0x20000020 0x20>,
			<&dma_blsp1 17 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in  = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
			 <&clock_gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_5_active>;
		pinctrl-1 = <&i2c_5_sleep>;
		status = "disabled";
	};

	i2c_6: i2c@7af5000 { /* BLSP2 QUP1 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x7af5000  0x600>;
		reg-names = "qup_phys_addr";
		interrupt-names = "qup_irq";
		interrupts = <0 299 0>;
		dmas = <&dma_blsp2 2 64 0x20000020 0x20>,
			<&dma_blsp2 3 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <84>;
		qcom,clk-freq-out = <400000>;
		qcom,clk-freq-in  = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
			 <&clock_gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_6_active>;
		pinctrl-1 = <&i2c_6_sleep>;
		status = "disabled";
	};

	spi_1: spi@78b5000 { /* BLSP1 QUP1 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x78b5000 0x600>,
		      <0x7884000 0x25000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 95 0>, <0 238 0>;
		spi-max-frequency = <50000000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <8>;
		qcom,bam-producer-pipe-index = <9>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_1_active>;
		pinctrl-1 = <&spi_1_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
			 <&clock_gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
		status = "disabled";
	};

	spi_2: spi@78b6000 { /* BLSP1 QUP2 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x78b6000 0x600>,
		      <0x7884000 0x25000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 96 0>, <0 238 0>;
		spi-max-frequency = <25000000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <10>;
		qcom,bam-producer-pipe-index = <11>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_2_mosi_a1_active
			&spi_2_miso_a1_active
			&spi_2_cs_n_a1_active
			&spi_2_clk_a1_active>;
		pinctrl-1 = <&spi_2_mosi_a1_sleep
			&spi_2_miso_a1_sleep
			&spi_2_cs_n_a1_sleep
			&spi_2_clk_a1_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
			 <&clock_gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
		status = "disabled";
	};

	spi_3: spi@78b7000 { /* BLSP1 QUP3 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x78b7000 0x600>,
		      <0x7884000 0x25000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 97 0>, <0 238 0>;
		spi-max-frequency = <25000000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <12>;
		qcom,bam-producer-pipe-index = <13>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_3_active>;
		pinctrl-1 = <&spi_3_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
			 <&clock_gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
		status = "disabled";
	};

	spi_4: spi@78b8000 { /* BLSP1 QUP4 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x78b8000 0x600>,
		      <0x7884000 0x25000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 98 0>, <0 238 0>;
		spi-max-frequency = <50000000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <14>;
		qcom,bam-producer-pipe-index = <15>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_4_active>;
		pinctrl-1 = <&spi_4_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
			 <&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
		status = "disabled";
	};

	spi_5: spi@78b9000 { /* BLSP1 QUP2 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x78b9000 0x600>,
		      <0x7884000 0x25000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 99 0>, <0 238 0>;
		spi-max-frequency = <50000000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <16>;
		qcom,bam-producer-pipe-index = <17>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_5_active>;
		pinctrl-1 = <&spi_5_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
			 <&clock_gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
		status = "disabled";
	};

	spi_6: spi@7af5000 { /* BLSP2 QUP1 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x7af5000 0x600>,
		      <0x7ac4000 0x17000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 299 0>, <0 239 0>;
		spi-max-frequency = <50000000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <2>;
		qcom,bam-producer-pipe-index = <3>;
		qcom,master-id = <84>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_6_active>;
		pinctrl-1 = <&spi_6_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
			 <&clock_gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
		status = "disabled";
	};


	blsp1_uart1_hs: uart@78af000 { /* BLSP1 UART1 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x78af000 0x200>,
		    <0x7884000 0x25000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart1_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 107 0
			    1 &intc 0 238 0
			    2 &tlmm 31 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;

		qcom,bam-tx-ep-pipe-index = <0>;
		qcom,bam-rx-ep-pipe-index = <1>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc GCC_BLSP1_UART0_APPS_CLK>,
		    <&clock_gcc GCC_BLSP1_AHB_CLK>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart1_sleep>;
		pinctrl-1 = <&blsp1_uart1_active>;

		qcom,msm-bus,name = "buart1";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			    <86 512 0 0>,
			    <86 512 500 800>;
		status = "disabled";
	};

	blsp1_uart2_hs: uart@78b0000{ /* BLSP1 UART2 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x78b0000 0x200>,
		    <0x7884000 0x25000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart2_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 108 0
			    1 &intc 0 238 0
			    2 &tlmm 23 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;

		qcom,bam-tx-ep-pipe-index = <2>;
		qcom,bam-rx-ep-pipe-index = <3>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>,
		    <&clock_gcc GCC_BLSP1_AHB_CLK>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart2_sleep>;
		pinctrl-1 = <&blsp1_uart2_active>;

		qcom,msm-bus,name = "buart2";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			    <86 512 0 0>,
			    <86 512 500 800>;
		status = "disabled";
	};

	blsp1_uart3_hs: uart@78b1000 { /* BLSP1 UART3 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x78b1000 0x200>,
		    <0x7884000 0x25000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart3_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 118 0
			    1 &intc 0 238 0
			    2 &tlmm 18 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;

		qcom,bam-tx-ep-pipe-index = <4>;
		qcom,bam-rx-ep-pipe-index = <5>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
		    <&clock_gcc GCC_BLSP1_AHB_CLK>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart3_sleep>;
		pinctrl-1 = <&blsp1_uart3_active>;

		qcom,msm-bus,name = "buart3";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			    <86 512 0 0>,
			    <86 512 500 800>;
		status = "disabled";
	};

	blsp1_uart4_hs: uart@78b2000 { /* BLSP1 UART4 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x78b2000 0x200>,
		    <0x7884000 0x25000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart4_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 119 0
			    1 &intc 0 238 0
			    2 &tlmm 83 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;

		qcom,bam-tx-ep-pipe-index = <6>;
		qcom,bam-rx-ep-pipe-index = <7>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc GCC_BLSP1_UART3_APPS_CLK>,
		    <&clock_gcc GCC_BLSP1_AHB_CLK>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart4_tx_sleep>,
			 <&blsp1_uart4_rxcts_sleep>, <&blsp1_uart4_rfr_sleep>;
		pinctrl-1 = <&blsp1_uart4_tx_active>,
			<&blsp1_uart4_rxcts_active>, <&blsp1_uart4_rfr_active>;

		qcom,msm-bus,name = "buart4";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			    <86 512 0 0>,
			    <86 512 500 800>;
		status = "disabled";
	};

	blsp2_uart1_hs: uart@7aef000 { /* BLSP1 UART4 */
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x7aef000 0x200>,
		    <0x7ac4000 0x17000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp2_uart1_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 297 0
			    1 &intc 0 239 0
			    2 &tlmm 27 0>;

		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;

		qcom,bam-tx-ep-pipe-index = <0>;
		qcom,bam-rx-ep-pipe-index = <1>;
		qcom,master-id = <84>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc GCC_BLSP2_UART0_APPS_CLK>,
		    <&clock_gcc GCC_BLSP2_AHB_CLK>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp2_uart1_sleep>;
		pinctrl-1 = <&blsp2_uart1_active>;

		qcom,msm-bus,name = "buart5";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			    <84 512 0 0>,
			    <84 512 500 800>;
		status = "disabled";
	};
};