/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include #include #include &soc { usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; reg = <0x0a600000 0x100000>; reg-names = "core_base"; iommus = <&apps_smmu 0x540 0x0>; #address-cells = <1>; #size-cells = <1>; ranges; interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>; interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", "ss_phy_irq", "dm_hs_phy_irq"; USB3_GDSC-supply = <&usb30_prim_gdsc>; dpdm-supply = <&qusb_phy0>; qcom,use-pdc-interrupts; clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "xo"; resets = <&clock_gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ 0x120 /* GSI_DBL_ADDR_H */ 0x130 /* GSI_RING_BASE_ADDR_L */ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ qcom,gsi-disable-io-coherency; qcom,dwc-usb3-msm-tx-fifo-size = <21288>; qcom,msm-bus,name = "usb0"; qcom,msm-bus,num-cases = <4>; qcom,msm-bus,num-paths = <3>; qcom,msm-bus,vectors-KBps = /* suspend vote */ , , , /* nominal vote */ , , , /* svs vote */ , , , /* min vote */ , , ; qcom,default-bus-vote = <2>; /* use svs bus voting */ dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; interrupts = <0 133 0>; usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; usb-core-id = <0>; tx-fifo-resize; maximum-speed = "super-speed"; dr_mode = "otg"; }; qcom,usbbam@a704000 { compatible = "qcom,usb-bam-msm"; reg = <0xa704000 0x17000>; interrupts = <0 132 0>; qcom,usb-bam-fifo-baseaddr = <0x146a6000>; qcom,usb-bam-num-pipes = <4>; qcom,disable-clk-gating; qcom,usb-bam-override-threshold = <0x4001>; qcom,usb-bam-max-mbps-highspeed = <400>; qcom,usb-bam-max-mbps-superspeed = <3600>; qcom,reset-bam-on-connect; qcom,pipe0 { label = "ssusb-qdss-in-0"; qcom,usb-bam-mem-type = <2>; qcom,dir = <1>; qcom,pipe-num = <0>; qcom,peer-bam = <0>; qcom,peer-bam-physical-address = <0x6064000>; qcom,src-bam-pipe-index = <0>; qcom,dst-bam-pipe-index = <0>; qcom,data-fifo-offset = <0x0>; qcom,data-fifo-size = <0x1800>; qcom,descriptor-fifo-offset = <0x1800>; qcom,descriptor-fifo-size = <0x800>; }; }; }; /* Primary USB port related QUSB2 PHY */ qusb_phy0: qusb@88e3000 { compatible = "qcom,qusb2phy-v2"; reg = <0x088e3000 0x400>, <0x00780258 0x4>, <0x088e7014 0x4>; reg-names = "qusb_phy_base", "efuse_addr", "refgen_north_bg_reg_addr"; qcom,efuse-bit-pos = <25>; qcom,efuse-num-bits = <3>; vdd-supply = <&pm6150_l4>; vdda18-supply = <&pm6150_l11>; vdda33-supply = <&pm6150_l17>; qcom,vdd-voltage-level = <0 880000 900000>; qcom,qusb-phy-reg-offset = <0x240 /* QUSB2PHY_PORT_TUNE1 */ 0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */ 0x210 /* QUSB2PHY_PWR_CTRL1 */ 0x230 /* QUSB2PHY_INTR_CTRL */ 0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */ 0x254 /* QUSB2PHY_TEST1 */ 0x198 /* PLL_BIAS_CONTROL_2 */ 0x27c /* QUSB2PHY_DEBUG_CTRL1 */ 0x280 /* QUSB2PHY_DEBUG_CTRL2 */ 0x284 /* QUSB2PHY_DEBUG_CTRL3 */ 0x288 /* QUSB2PHY_DEBUG_CTRL4 */ 0x2a0>; /* QUSB2PHY_STAT5 */ qcom,qusb-phy-init-seq = /* */ <0x23 0x210 /* PWR_CTRL1 */ 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ 0x80 0x2c /* PLL_CMODE */ 0x0a 0x184 /* PLL_LOCK_DELAY */ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ 0x22 0x198 /* PLL_BIAS_CONTROL_2 */ 0x21 0x214 /* PWR_CTRL2 */ 0x08 0x220 /* IMP_CTRL1 */ 0x58 0x224 /* IMP_CTRL2 */ 0x47 0x240 /* TUNE1 */ 0x28 0x244 /* TUNE2 */ 0xca 0x248 /* TUNE3 */ 0x04 0x24c /* TUNE4 */ 0x03 0x250 /* TUNE5 */ 0x30 0x23c /* CHG_CTRL2 */ 0x22 0x210>; /* PWR_CTRL1 */ qcom,qusb-phy-host-init-seq = /* */ <0x23 0x210 /* PWR_CTRL1 */ 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ 0x80 0x2c /* PLL_CMODE */ 0x0a 0x184 /* PLL_LOCK_DELAY */ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ 0x22 0x198 /* PLL_BIAS_CONTROL_2 */ 0x21 0x214 /* PWR_CTRL2 */ 0x08 0x220 /* IMP_CTRL1 */ 0x58 0x224 /* IMP_CTRL2 */ 0x47 0x240 /* TUNE1 */ 0x28 0x244 /* TUNE2 */ 0xca 0x248 /* TUNE3 */ 0x04 0x24c /* TUNE4 */ 0x03 0x250 /* TUNE5 */ 0x30 0x23c /* CHG_CTRL2 */ 0x22 0x210>; /* PWR_CTRL1 */ phy_type= "utmi"; clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; clock-names = "ref_clk_src", "cfg_ahb_clk"; resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; }; /* Primary USB port related QMP USB DP Combo PHY */ usb_qmp_dp_phy: ssphy@88e8000 { compatible = "qcom,usb-ssphy-qmp-dp-combo"; reg = <0x88e8000 0x3000>; reg-names = "qmp_phy_base"; vdd-supply = <&pm6150_l4>; qcom,vdd-voltage-level = <0 880000 900000>; core-supply = <&pm6150l_l3>; qcom,vbus-valid-override; qcom,qmp-phy-init-seq = /* */ ; qcom,qmp-phy-reg-offset = ; clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; clock-names = "aux_clk", "pipe_clk", "ref_clk_src", "ref_clk", "com_aux_clk", "cfg_ahb_clk"; resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "global_phy_reset", "phy_reset"; }; usb_audio_qmi_dev { compatible = "qcom,usb-audio-qmi-dev"; iommus = <&apps_smmu 0x100f 0x0>; qcom,usb-audio-stream-id = <0xf>; qcom,usb-audio-intr-num = <2>; }; };