system_rev is meant for board revision, this patch changes
all relevant instances to use the new omap_rev() function
liberating system_rev to be used with ATAG_REVISION as it
has been designed.
Signed-off-by: Lauri Leukkunen <lauri.leukkunen@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
At some point omap2 changed the bits for GET_OMAP_CLASS, which
broke 15xx detection on 730 as noticed by Russell King.
This patch fixes omap2 cpu detection to respect the original
GET_OMAP_CLASS, and simplifies the detection for 34xx.
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch integrates the OMAP3 clock tree with the clockdomain code.
This patch:
- marks OMAP34xx clocks with their corresponding clockdomain.
- adds code to convert the clockdomain name to a clockdomain pointer in the
struct clk during clk_register().
- modifies OMAP2 clock usecounting to call into the clockdomain code
when clocks are enabled or disabled.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch creates an interface to the powerdomain registers in the
PRM/CM modules on OMAP2/3. This interface is intended to be used by
PM code, e.g., pm.c; not by device drivers directly.
Each powerdomain will be defined in later patches as static
structures. Also defined are dependencies between powerdomains,
used for adding and removing PM_WKDEP and CM_SLEEPDEP bits. The
powerdomain structures are linked into a list at boot by
pwrdm_register(), similar to the OMAP clock code.
The patch adds a Kconfig option, CONFIG_OMAP_DEBUG_POWERDOMAIN, which
when enabled will emit verbose debug messages via pr_debug().
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds support for DPLL autoidle control to the OMAP3 clock
framework. These functions will be used by the noncore DPLL enable
and disable code - this is because, according to the CDP code, the
DPLL autoidle status must be saved and restored across DPLL
lock/bypass/off transitions.
N.B.: the CORE DPLL (DPLL3) has three autoidle mode options, rather
than just two. This code currently does not support the third option,
low-power bypass autoidle.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
These changes is the result of the discussion with Paul Walmsley.
His ideas are included into this patch.
Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks,
and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk).
omap2_get_dpll_rate() now returns the correct DPLL rate, as represented
by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along
with high-frequency bypass support.
Add support for DPLLs function in locked and bypass clock modes.
Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Lauri Leukkunen