15 Commits (edd711f3810f46787593fb79eda9a9fbb82cbb62)

Author SHA1 Message Date
Maciej W. Rozycki 9cf8ff9644 [MIPS] Fix CPU type bitmasks for MIPS III, IV and V. 19 years ago
Ralf Baechle 0401572a9b MIPS: Reorganize ISA constants strictly as bitmasks. 19 years ago
Ralf Baechle b4672d3729 MIPS: Introduce machinery for testing for MIPSxxR1/2. 19 years ago
Ralf Baechle e7958bb90d MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1. 19 years ago
Andrew Isaacson 93ce2f524e Add support for SB1A CPU. 19 years ago
Ralf Baechle 02cf211968 Cleanup the mess in cpu_cache_init. 19 years ago
Maciej W. Rozycki 98e316d4b1 Move MIPS Technologies processor IDs to where they belong. 19 years ago
Pete Popov bdf21b18b4 Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it. 19 years ago
Ralf Baechle 8f40611d2b Detect the MIPS R2 vectored interrupt, external interrupt controller 19 years ago
Ralf Baechle bbc7f22f6d Detect the 34K. 19 years ago
Ralf Baechle e50c0a8fa6 Support the MIPS32 / MIPS64 DSP ASE. 19 years ago
Ralf Baechle 4194318c39 Cleanup decoding of MIPSxx config registers. 19 years ago
Pete Popov e3ad1c23ba Base Au1200 2.6 support. 19 years ago
Ralf Baechle 55a6feb671 Add a few more PrId vendor IDs. 19 years ago
Linus Torvalds 1da177e4c3 Linux-2.6.12-rc2 20 years ago