Due to a hardware bug, the originally assigned range cannot reliably
be used for boot configuration and must not be modifiable through
ethtool.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Include PMA/PMD in loopback self-tests as intended.
Add NVRAM checksum validation and include it in self-tests.
Add register self-tests.
Run PHY self-tests where available.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Some functions return an error code which is always 0. Change their
return types to void and simplify their callers accordingly.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Extend the SPI device setup code to support this.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Replace (cond ? 1 : 0) with cond or !!cond as appropriate, and
(cond ? 0 : 1) with !cond.
Remove some redundant boolean temporaries.
Rename one field that looks like a flag but isn't.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Checksum generation is an attribute of our hardware TX queues, not TX
descriptors. We previously used a single queue and turned checksum
generation on or off as requested through ethtool. However, this can
result in regenerating checksums in raw packets that should not be
modified. We now create 2 hardware TX queues with checksum generation
on or off. They are presented to the net core as one queue since it
does not know how to select between them.
The self-test verifies that a bad checksum is unaltered on the queue
with checksum generation off.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Use of the net_device::priv field is deprecated.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Add a set of self-tests accessible thorugh ethtool.
Add hardware loopback and TX disable control code to support them.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
The SFC4000 controller does not have hardware support for TSO, and the
core GSO code incurs a high cost in allocating and freeing skbs. This
TSO implementation uses lightweight packet header structures and is
substantially faster.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
The driver supports the 10Xpress PHY and XFP modules on our reference
designs SFE4001 and SFE4002 and the SMC models SMC10GPCIe-XFP and
SMC10GPCIe-10BT.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Ben Hutchings