Commit Graph

9 Commits (de4b21474053513d9ad41994c95dade3e6b3362f)

Author SHA1 Message Date
Mike Frysinger 315a8e34f7 Blackfin arch: setup aliases for some core Core A MMRs 18 years ago
Bryan Wu c04d66bbbd Blackfin arch: clean up some coding style issues 18 years ago
Michael Hennerich 5610db61cf Blackfin arch: Add Support for Peripheral PortMux and resouce allocation 18 years ago
Michael Hennerich 1c5d2265a8 Blackfin arch: add missing implementations SIC_IWR crosses several registers 18 years ago
Roy Huang 24a07a1241 Blackfin arch: initial supporting for BF548-EZKIT 18 years ago
Mike Frysinger 9c8f1729b0 Blackfin arch: add missing braces around array bfin serial init 18 years ago
Bryan Wu 19381f024b Blackfin arch: update blackfin header files to latest one in VDSP. 18 years ago
Michael Hennerich d1b945fdb6 Blackfin arch: Move write to VR_CTL closer to IDLE 18 years ago
Bryan Wu 1394f03221 blackfin architecture 18 years ago