Update coretemp supported CPU TjMax lists and some cleanup work.
Signed-off-by: Chen Gong <gong.chen@linux.intel.com>
Cc: Rudolf Marek <r.marek@assembler.cz>
Cc: Huaxu Wan <huaxu.wan@intel.com>
Cc: Jean Delvare <khali@linux-fr.org>
Cc: Guenter Roeck <guenter.roeck@ericsson.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Add Lynnfield processor support. Lynnfield is a quad-core Nehalem
based microprocessor for Desktop market, which is introduced in
September 2009.
Signed-off-by: Huaxu Wan <huaxu.wan@linux.intel.com>
Signed-off-by: Kent Liu <kent.liu@linux.intel.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Following patch adds support for mobile Penryn CPUs. Intel documents this
poorly. I asked the Coretemp author for some help. This is totally untested and
may not work. Please test!
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Cc: Huaxu Wan <huaxu.wan@linux.intel.com>
Cc: Kent Liu <kent.liu@linux.intel.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Fix Atom CPUs support. Intel documents TjMax at 90 degrees C but
some Atoms may have 125 degrees C (this is undocumented speculation).
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Cc: Huaxu Wan <huaxu.wan@linux.intel.com>
Cc: Kent Liu <kent.liu@linux.intel.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
This patch adds support for family 0x17, which has Penryn Core. It should also
cover the 8 cores Xeons.
Can someone test please? I think it should work.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Mark M. Hoffman <mhoffman@lightlink.com>
Following patch will add reporting of maximum temperature, at which all fans
should spin full speed. It may be non-physical temperature on Desktop/Server CPUs.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Mark M. Hoffman <mhoffman@lightlink.com>
This patch adds support for the Celeron 4xx based on Core 2 core.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Mark M. Hoffman <mhoffman@lightlink.com>
Chen Gong