It should be ok to pass in NULL for some kobject functions, so add error
checking for all exported kobject functions to be more robust.
Cc: Kay Sievers <kay.sievers@vrfy.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
drivers/ide/ide-acpi.c: In function 'ide_acpi_get_timing':
drivers/ide/ide-acpi.c:537: warning: format '%x' expects type 'unsigned int', but argument 4 has type 'long unsigned int'
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This patch implements ACPI integration for generic IDE devices.
The ACPI spec mandates that some methods are called during suspend and
resume. And consequently there most modern Laptops cannot resume
properly without it.
According to the spec, we should call '_GTM' (Get Timing) upon suspend
to store the current IDE adapter settings.
Upon resume we should call '_STM' (Set Timing) to initialize the
adapter with the stored settings; afterwards '_GTF' (Get Taskfile)
should be called which returns a buffer with some IDE initialisation
commands. Those commands should be passed to the drive.
There are two module params which control the behaviour of this patch:
'ide=noacpi'
Do not call any ACPI methods (Disables any ACPI method calls)
'ide=acpigtf'
Enable execution of _GTF methods upon resume.
Has no effect if 'ide=noacpi' is set.
'ide=acpionboot'
Enable execution of ACPI methods during boot.
This might be required on some machines if 'ide=acpigtf' is
selected as some machines modify the _GTF information
depending on the drive identification passed down with _STM.
Signed-off-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
On Thursday 11 January 2007 23:17, Bartlomiej Zolnierkiewicz wrote:
>
> My working IDE tree (against Linus' tree) now resides here:
>
> http://kernel.org/pub/linux/kernel/people/bart/pata-2.6/patches/
Bart, here's a driver I've been keeping out-of-tree for the past couple
of years. This is for the Delking/Lexar/ASKA/etc.. 32-bit cardbus IDE
CompactFlash adapter card.
It's probably way out of sync with the latest driver model (??), but it
still builds/works. I'm not interested in doing much of a rewrite, other
than for libata someday, as I no longer use the card myself.
But lots of other people do seem to use it, so it might be nice to see it
"in-tree".
Signed-off-by: Mark Lord <mlord@pobox.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
* set ATAPI/IORDY/TIME bits correctly in it8213_tuneproc()
* fix UDMA/MWDMA/SWDMA masks in it8213_init_hwif()
* in it8213_tune_chipset() SWDMA2 mode should be used instead of MWDMA0
* backport various fixes from piix/slc90e66 drivers:
- in it8213_tuneproc() the highest possible PIO mode is PIO4 (not PIO5)
- clear ATAPI/IORDY/TIME bits before setting them also for slave device
- use ->speedproc in it8213_config_drive_for_dma()
- don't try to tune PIO in config_chipset_for_pio()
- simplify is_slave calculation in it8213_tuneproc()
- misc cleanups
* fix it8213_ratemask() and it8213_tuneproc() comments
* simplify it8213_init_hwif()
* remove init_chipset_it8213()
* add missing Copyrights and update MODULE_AUTHOR()
* CodingStyle cleanups
* remove dead code
v2:
* PCI_DEVICE_ID_ITE_8213 is only defined in -mm kernels,
so just use PCI Device ID (0x8213) directly
* fix ->ultra_mask incorrectly changed to 0x3f in v1 version of the patch
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This is the driver for the Toshiba TC86C001 GOKU-S PCI IDE controller,
completely reworked from the original brain-damaged Toshiba's 2.4 version.
This single channel UltraDMA/66 controller is very simple in programming,
yet Toshiba managed to plant many interesting bugs in it. The particularly
nasty "limitation 5" (as they call the errata) caused me to abuse the IDE
core in a possibly most interesting way so far. However, this is still
better than the #ifdef mess in drivers/ide/ide-io.c that the original
version included (well, it had much more mess)...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Acked-by: Alan Cox <alan@redhat.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Fold check_in_drive_lists() into quirkproc() handler in both PDC202xx
drivers-- this function was never called with a list other than
pdc_quirk_drives and was a bad example of code overall...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Remove the following useless fragments from the driver:
- the ide_dma_lostirq() and ide_dma_timeout() handlers which boil down to just
printing the incoherent reset message and calling their default counterparts;
- check for non-NULL drive->id in the ide_dma_check() handler -- this is assumed
to be true by all other handlers (also, get rid of unnecessary nesting of the
conditional statements there);
- the comment before pdcnew_tune_drive() which has nothing to do with the code.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Synchronize with version 0.46 of the Intel PIIX/ICH driver:
- carry over Alan's and my own fixes in the tuneproc() method and my cleanups
both there and in the ratemask() method;
- SLC90E66 only supports MW DMA modes 1/2 and SW DMA mode 2 (just like Intel
chips), so don't claim support for other MW/SW DMA modes;
- don't check dor non-NULL drive->id in the ide_dma_check() method -- this is
assumed to be true in all other drivers;
- do some coding/formatting cleanups while at it...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Fix/cleanup the driver's tuneproc() and ratemask() methods:
- PPE, IE, and TIME bits need to be cleared beforehand for the slave drive as
well as master (Alan probably just forgot about it);
- this driver only supports PIO modes up to 4, so must pass the correct limit
to ide_get_best_pio_mode();
- use min_t() macro instead of min();
- simplify slave vs master drive evaluation;
- do come coding and formatting cleanups...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
According to the datasheet, Intel 82371MX (MPIIX) actually has only a
single IDE channel mapped to the primary or secondary ports depending on
the value of the bit 14 of the IDETIM register at PCI config. offset 0x6C
(the register at 0x6F which the driver refers to. doesn't exist). So,
disguise the controller as dual channel and set enablebits masks/values
such that only either primary or secondary channel is detected enabled.
Also, preclude the IDE probing code from reading PCI BARs, this controller
just doesn't have them (it's not the separate PCI function like the other
PCI controllers), it only decodes the legacy addresses.
[ Alan sayeth " MPIIX does not work with or without the change. It needs its
own different driver and not to use setup-pci. Huge job and since it works
well with libata who cares. Ditto the early PIIX chip." ]
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Fix minor coding mistake in the HPT36x PCI clock detection code noticed by
Bartlomiej Zolnierkiewicz -- it always reported 33 MHz due to the missing
'break' statements. This, however, most probably never mattered -- in fact, I
was thinking of removing the 25/40 MHz cases completely since HPT36x BIOSes
didn't seem to set any other value than 7 into the 'cmd_high_time' field, i.e.
supported only 33 MHz PCI.
Note that in the original driver there was another bug: 25 and 40 MHz cases
were interchanged. Since the 'cmd_high_time' field is in units of PCI clocks,
a lower clock count just *cannot* correspond to a higher frequency, i. e. it
should be 5 for 25 MHz PCI and 9 for 40 MHz PCI, not the other way around.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Finally, rework the driver init. code to correctly handle all the chip
variants HighPoint has created so far. This should cure the rest of the
timing issues in the driver (especially, on 66 MHz PCI) caused by the
HighPoint's habit of switching the base DPLL clock with every new revision
of the chips...
- switch to using the enumeration type to differ between the numerous chip
variants, matching PCI device/revision ID with the chip type early, at the
init_setup stage;
- extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
stop duplicating it for each channel by storing the pointer in the pci_dev
structure: first, at the init_setup stage, point it to a static "template"
with only the chip type and its specific base DPLL frequency, the highest
supported DMA mode, and the chip settings table pointer filled, then, at
the init_chipset stage, allocate per-chip instance and fill it with the
rest of the necessary information;
- get rid of the constant thresholds in the HPT37x PCI clock detection code,
switch to calculating PCI clock frequency based on the chip's base DPLL
frequency;
- switch to using the DPLL clock and enable UltraATA/133 mode by default on
anything newer than HPT370/A;
- fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
unify the HPT36x/37x setup code and the speedproc handlers by joining the
register setting lists into the table indexed by the clock selected;
- add enablebits for all the chips to avoid touching disabled channels
(though the HighPoint BIOS seem to only disable the primary one on
HPT371/N);
- separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
when setting an UltraDMA mode in hpt37x_tune_chipset().
This version has been tested on HPT370/302/371N.
Thanks to Alan for the inspiration. Hopefully, his libata driver will also
benefit from the work done on this "obsolete" driver...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Clean up DMA timeout handling for HPT370:
- hpt370_lostirq_timeout() cleared the DMA status which made __ide_dma_end()
called afterwards return the incorrect result, and the DMA engine was reset
both before and after stopping DMA while the HighPoint drivers only do it
after (which seems logical) -- fix this and also rename the function;
- get rid of the needless mutual recursion in hpt370_ide_dma_end() and
hpt370_ide_dma_timeout();
- get rid of hpt370_lostirq_timeout() since hwif->ide_dma_end() called from
the driver's interrupt handler later does all its work.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Continue with the driver rewrite:
- move the interrupt twiddling code from the speedproc handlers into the
init_hwif_hpt366 which allows to merge the two HPT37x speedproc handlers
into one;
- get rid of in init_hpt366 which solely consists of the duplicate code, then
fold init_hpt37x() into init_chipset_hpt366();
- fix hpt3xx_tune_drive() to always set the PIO mode requested, not the best
possible one, change hpt366_config_drive_xfer_rate() accordingly, simplify
it a bit;
- group all the DMA related code together init_hwif_hpt366(), and generally
clean up and beautify it.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Begin the real driver redesign. For the starters:
- cache the offset of the IDE channel's MISC. control registers which are used
throughout the driver in hwif->select_data;
- only touch the relevant MCR when detecting the cable type on HPT374's
function 1;
- make HPT36x's speedproc handler look the same way as HPT37x ones; fix the
PIO timing register mask for HPT37x.
- rename all the HPT3xx register related variables consistently; clean up the
whitespace.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Switch to using pci_get_slot() to get to the function 1 of HPT36x/374 chips --
there's no need for the driver itself to walk the list of the PCI devices, and
it also forgets to check the bus number of the device found.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
- Rework the driver setup code so that it prefixes the driver startup
messages with the real chip name.
- Print the measured f_CNT value and the DPLL setting for non-HPT3xx
chips as well.
- Claim the extra 240 bytes of I/O space for all chips, not only for
those having PCI device ID of 0x0004.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
- Rework hpt3xx_ratemask() and hpt3xx_ratefilter() so that the former
returns the max. mode computed at the load time and doesn't have to do
bad Ultra33 drive list lookups anymore; remove the duplicate code from
the latter function. Move the quirky drive list lookup into
hpt3xx_quirkproc() where it should have been from the start...
- Disable UltraATA/100 for HPT370 by default as the 33 MHz ATA clock
being used does not allow for it, and this *greatly* increases the
transfer speed.
- Save some space by using byte-wide fields in struct hpt_info; switch to
reading the 8-bit PCI revision ID reg. only, not the whole 32-bit reg.
- Start incrementing the driver version number with each patch (should
have been done from the first one posted).
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/shaggy/jfs-2.6:
JFS: Remove incorrect kgdb define
JFS: call io_schedule() instead of schedule() to avoid deadlock
JFS: Add lockdep annotations
JFS: Avoid BUG() on a damaged file system
* git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-2.6-nmw: (57 commits)
[GFS2] make gfs2_writepages() static
[GFS2] Unlock page on prepare_write try lock failure
[GFS2] nfsd readdirplus assertion failure
[DLM] fix softlockup in dlm_recv
[DLM] zero new user lvbs
[DLM/GFS2] indent help text
[GFS2] Fix unlink deadlocks
[GFS2] Put back semaphore to avoid umount problem
[GFS2] more CURRENT_TIME_SEC
[GFS2/DLM] fix GFS2 circular dependency
[GFS2/DLM] use sysfs
[GFS2] make lock_dlm drop_count tunable in sysfs
[GFS2] increase default lock limit
[GFS2] Fix list corruption in lops.c
[GFS2] Fix recursive locking attempt with NFS
[DLM] can miss clearing resend flag
[DLM] saved dlm message can be dropped
[DLM] Make sock_sem into a mutex
[GFS2] Fix typo in glock.c
[GFS2] use CURRENT_TIME_SEC instead of get_seconds in gfs2
...
On Mon, Jan 29, 2007 at 08:45:28PM -0800, Andrew Morton wrote:
>...
> Changes since 2.6.20-rc6-mm2:
>...
> git-gfs2-nmw.patch
>...
> git trees
>...
This patch makes the needlessly global gfs2_writepages() static.
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Steven Whitehouse <swhiteho@redhat.com>
When the try lock of the glock failed in prepare_write we were
incorrectly exiting this function with the page still locked.
This was resulting in further I/O to this page hanging.
Signed-off-by: Steven Whitehouse <swhiteho@redhat.com>
When we do full FP emulation its possible that we need to post a SIGFPE based
on the results of the emulation. The previous code ignored this case completely.
Additionally, the Soft_emulate_8xx case had two issues. One, we should never
generate a SIGFPE since the code only does data movement. Second, we were
interpreting the return codes incorrectly, it returns 0 on success, 1 on
illop and -EFAULT on a data access error.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Anytime we are emulating an instruction we are going to be doing some form of
get_user() to get the instruction image to decode. Since get_user() might
sleep we need to ensure we have interrupts enabled or we might see something
like:
Debug: sleeping function called from invalid context at arch/powerpc/kernel/traps.c:697
in_atomic():0, irqs_disabled():1
Call Trace:
[D6023EB0] [C0007F84] show_stack+0x58/0x174 (unreliable)
[D6023EE0] [C0022C34] __might_sleep+0xbc/0xd0
[D6023EF0] [C000D158] program_check_exception+0x1d8/0x4fc
[D6023F40] [C000E744] ret_from_except_full+0x0/0x4c
--- Exception: 700 at 0x102a7100
LR = 0xdb9ef04
However, we want to ensure that interrupts are disabled when handling a trap
exception that might be used for a kernel breakpoint. This is why ProgramCheck
is marked as EXC_XFER_STD instead of EXC_XFER_EE.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Added kprobes to ppc32 platforms that have use single_step_exception. This
excludes 4xx and anything Book-E since their debug mechanisms for single stepping
are completely different.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
H_BULK_REMOVE lets us remove 4 entries from the MMU hash table with one
hypervisor call. This uses it in pSeries_lpar_hpte_invalidate so we
can tear down mappings with fewer hypervisor calls.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Some instruction tracing tools use the RI (recoverable interrupt) bit
in the MSR to indicate when it's safe to single-step. Currently we
clear RI after restoring r13 when returning to userspace. However,
if we single-step past the point where r13 is restored, we'll corrupt
r13 in the exception entry code and not restore it. This moves the
clearing of RI to just before r13 is restored so this doesn't happen.
Signed-off-by: Paul Mackerras <paulus@samba.org>
To the issue: some point during 2.6.20 development, Paul Mackerras
introduced the "lazy IRQ disabling" patch (very cool work, BTW).
In that patch, the performance monitor unit exception was marked as
"maskable", in the sense that if interrupts were soft-disabled, that
exception could be ignored. This broke my PowerPC profiling code.
The symptom that I see is that a varying number of interrupts
(from 0 to $n$, typically closer to 0) get delivered, when, in
reality, it should always be very close to $n$.
The issue stems from the way masking is being done. Masking in
this fashion seems to work well with the decrementer and external
interrupts, because they are raised again until "really" handled.
For the PMU, however, this does not apply (at least on my Xserver
machine with a 970FX processor). If the PMU exception is not handled,
it will _not_ be re-raised (at least on my machine). The documentation
states that the PMXE bit in MMCR0 is set to 0 when the PMU exception
is raised. However, software must re-set the bit to re-enable PMU
exceptions. If the exception is ignored (as currently) not only is
that interrupt lost, but because software does not re-set PMXE, the
PMU registers are "frozen" forever.
[This patch means that performance monitor exceptions are taken and
handled even if irqs are off, as long as some other interrupt hasn't
come along and caused interrupts to be hard-disabled. In this sense
the PMU exception becomes like an NMI. The oprofile code for most
powerpc processors does nothing that is unsafe in an NMI context, but
the Cell oprofile code does a spin_lock_irqsave. However, that turns
out to be OK because Cell doesn't actually use the performance
monitor exception; performance monitor interrupts come in as a
regular interrupt on Cell, so will be disabled when irqs are off.
-- paulus.]
Signed-off-by: Paul Mackerras <paulus@samba.org>
The new dcr code does not currently compile when configured for native
DCR access on ARCH=powerpc. This patch fixes the problems.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Some systems supported by the maple platform (e.g. JS2x blades running
SLOF) are able to use the mmio_nvram backend for reading and writing
nvram. This is an improvement over the current situation -- no nvram
access from userspace at all.
Select MMIO_NVRAM for the maple platform.
Initialize the mmio_nvram backend from maple setup code.
Signed-off-by: Nathan Lynch <ntl@pobox.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Base pasemi defconfig. Nothing special, just the native drivers plus
common PCI-express/PCI cards.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
The DMA controller on PWRficient is somewhat special -- has a PCI header
so it looks like it's on the root PCI (-Express) root bus, but it uses
more than the default number of interrupts (and they are hardwired).
We need to wire up all interrupts for the DMA controller. The generic
IRQ code will only map the primary interrupt from the PCI header (128),
so add 129->211 by hand.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Timebase update is simple on PA6T, since global updates can be done from
one core by writing to an SPR.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Implement reset on platforms/pasemi. Default is just to reset the
cpu using the SDC registers.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Powersave support on PA6T. Right now it only uses 'doze' mode, and
will default to no savings (spin).
Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Early debug output for PA Semi UART. Uses the 2.05 CI real mode ops.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
G3 Blue & White is misconfigured by default so that CardBus controllers
in PCI slots don't work. The PCI bridge is programmed to only allow
access to bus 1 but not higher busses.
The patch forces the PCI busses to be reassigned if a Grackle controller
is found and the machine identifies itself as "PowerMac1,1"
Signed-off-by: Pavel Roskin <proski@gnu.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This patch adds base support for Celleb platform.
Signed-off-by: Kou Ishizaki <kou.ishizaki@toshiba.co.jp>
Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Spu management ops in arch/platforms/cell/spu_priv1_mmio.h can be used
commonly in of based platform. This patch separates spu management ops
from native cell code and uses on celleb platform.
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Kou Ishizaki <kou.ishizaki@toshiba.co.jp>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Greg Kroah-Hartman