The JMPRS register on Malta boards keeps a 32-bit CPU-endian
value. The readw() function assumes that the value it reads is a
little-endian 16-bit number. Therefore, using readw() to obtain
the value of the JMPRS register is a mistake. This error leads
to incorrect reading of the PCI clock frequency on big-endian
during board start-up.
Change readw() to __raw_readl().
This was tested by injecting a call to printk() and verifying
that the value of the jmpr variable was consistent with current
setting of the JP4 "PCI CLK" jumper.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
I noticed that the commit f197465384
(MIPS Tech: Get rid of volatile in core code) broke the software
reset functionality for MIPS Malta boards in big-endian mode.
According to the MIPS Malta board user's manual, writing the magic
32-bit GORESET value into the SOFTRES register initiates board soft
reset. My experimentation has shown that the endianness of the GORESET
integer should thereby be the same as the endianness, which has been
set for the CPU itself. The writew() function used to write the magic
value in the code introduced by the commit mentioned above, however,
swaps bytes for big-endian kernels and transfers 16 bits instead of 32.
The patch below replaces the writew() function by the __raw_writel()
routine, which leaves the byte order intact and transfers the whole
MIPS machine word. Trivial code cleanup (replacing spaces by a tab
and cutting oversized lines to make checkpatch.pl happy) is also
included.
The patch was tested using a Malta evaluation board running in both
BE and LE modes. For both modes, software reset was fully functional
after the change.
P.S. I suspect that the same commit broke the "standby" functionality
for MIPS Atlas boards. However, I did not touch the Atlas code as I
don't have such board at my disposal and also because the linux-mips.org
Web site claims that Atlas support is scheduled for removal.
Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The kernel currently only supports broadcasting of the timer interrupt
from a single timer, not multicasting into two multicast groups of
processors. So the implemented mechanism for SMTC works by broadcasting
the cp0 compare interrupt on VPE 0 and ignoring it on any additional VPEs.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Hard to follow who is pointing what to where and why so it's simply getting
in the way of the time code renovation.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Fairly cosmetic as it would only affect VSMP / SMTC kernels that don't
use vectored interrupts.
Found by Beth.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS doesn't do CPU hotplugging yet but since many of the functions don't
even have an __init let's fix this right.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
early_serial_setup was removed from serial.h, but forgot to put in
serial_8250.h
Signed-off-by: Yinghai Lu <yinghai.lu@sun.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
For some platforms it's definitions may conflict. So that's the one-liner.
The rest is 10 square kilometers of collateral damage fixup this include
used to paper over.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Support for performance counter overflow interrupt that is on a separate
interrupt from the timer.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
And an attempt to tidy up the core/controller differences.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Aside of being handy for debugging this has never been a particularly
good idea but is now getting in the way of dyntick / tickless kernels
and general cleanups.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch has merged GT64111 PCI routines and GT64120 PCI_0 routines.
GT64111 PCI is almost the same as GT64120's PCI_0.
This patch don't change GT64120 PCI routines.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
If R4k counter was used for hpt_timer and interrupt source,
c0_hpt_timer_init() initializes the c0_compare register.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Many Makefiles in arch/mips have EXTRA_AFLAGS := $(CFLAGS) line. This
is redundant while AFLAGS contains $(cflags-y) and any options only
listed in CFLAGS (not in cflags-y) should be unnecessary for asm
sources.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The "typename" field was obsoleted by the "name" field.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Current prom_free_prom_memory() implementations are almost same as
free_init_pages(), or no-op. Make free_init_pages() extern (again)
and make prom_free_prom_memory() use it.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Dmitri Vorobiev