2 Commits (c2f828977ba5d17c13debba374ea252d18e5ccfb)

Author	SHA1	Message	Date
Catalin Marinas	0762097625	[ARM] 4500/1: Add locking around the background L2x0 cache operations ... The background operations of the L2x0 cache controllers are aborted if another operation is issued on the same or different core. This patch protects the maintenance operation issuing/polling with a spinlock. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>	18 years ago
Catalin Marinas	382266ad5a	[ARM] 4135/1: Add support for the L210/L220 cache controllers ... This patch adds the support for the L210/L220 (outer) cache controller. The cache range operations are done by index/way since L2 cache controller only accepts physical addresses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>	18 years ago