Patch from Lennert Buytenhek
The ixp2000 defconfigs are among the few that do not enable module
support by default. I keep enabling module support by hand for every
new kernel version, so let's just make this change upstream.
Signed-off-by: Lennert Buytenhek
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Patch from Vincent Sanders
This fixes the "multiple definitions of cpufreq_get" build faliure on
the hackkit SA1100 platform.
Signed-off-by: Vincent Sanders
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Patch from Vincent Sanders
This fixes the "multiple definitions of cpufreq_get" build faliure on
the Badge4 SA1100 platform.
Signed-off-by: Vincent Sanders
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Patch from Dave Neuer
This fixes the "multiple definitions of cpufreq_get" errors on
StrongARM-based iPAQs.
Signed-off-by: Dave Neuer
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Patch from Lennert Buytenhek
The IXDP2800 is an evalution platform for the IXP2800 processor that
has two IXP2800s connected to the same PCI bus. This is problematic
as both CPUs will try to configure the PCI bus as they boot linux.
Contrary to on the other IXP2000 platforms, the boot loader on the
IXDP2800 doesn't configure the PCI bus properly, so we do want the
linux instance on one of the CPUs to do that.
Making one of the CPUs ignore the PCI bus (and thus act like a pure
PCI slave device) is not an option because there is a 82559 NIC on
the PCI bus for each of the CPUs.
The chosen solution is to have the master CPU configure the PCI bus
while the slave is kept in a quiescent state, and then to have the
slave CPU scan the PCI bus (without assigning resources) while the
master is kept in a quiescent state. After this ritual, the master
deletes the slave NIC from its PCI device list, the slave deletes
the master NIC from its device list, and (almost) all is well.
There's still one little problem: each of the CPUs has a 1G SDRAM
BAR, but the IXP2000 only has 512M of outbound PCI memory window.
We solve this by hand-assigning the master and slave SDRAM BARs to
a location outside each of the IXP's outbound PCI windows, and by
having the rest of the BARs autoconfigured in the outbound PCI
windows, in the range [e0000000..ffffffff], so that there is a 1:1
pci:phys mapping between them.
Even with this patch, a number of issues still remain -- just imagine
what happens if one of the CPUs is rebooted, by watchdog or by hand,
but the other one isn't. But those issues are not easily fixable
given the strange PCI layout of this board and the behavior of the
boot loader shipped with the platform.
Signed-off-by: Lennert Buytenhek
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Lennert Buytenhek