Set valid mac address to true only if mac address
programmed in fuse register valid.
Change-Id: I464b81a8b8728f36f93bed732e9c58495db4a4de
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Check phydev for null in case MAC2MAC enabled.
Change-Id: I728fc74ad680f4eca0e7eb8d83bfb38343ee7e26
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Set the phy irq from POLL to INTR mode and make sure
the register are set correctly.
Change-Id: I8ed06b0029920fcd003b008b188bdbe00467a03d
Acked-by: Abhishek Chauhan <abchauha@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Add support to provide only 1 argument as part
of disable . Speed argument is not needed to disable
loopback.
Change-Id: I442bb61dccc17bed30014d0c3eca2e14cdf9a8fd
Signed-off-by: Suraj Jaiswal <jsuraj@codeaurora.org>
The driver gets efuse address from device tree property.
It then read mac address 6 bytes from this address and
validates it. If the address is valid it is saved for
future use as appropriate.
Change-Id: Ic25183a7834182cf6671dca2f96431c70fd936ee
Signed-off-by: Rishi Gupta <rishgupt@codeaurora.org>
Dont include ipa header file as IPA offlaod
will not be enabled on IVI targets.
Change-Id: Ieb0ec605068a22a73e36d8ecaa49116d48cf5338
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Replace place_marker with update_marker api to capture
suspend resume kpi of pheripherals like usb, ethernet and
pcie.
Change-Id: Ida46d41273967aa5efccd06f13f6219adfba4a4e
Signed-off-by: Sanjay Dwivedi <sanjaykd@codeaurora.org>
Add new variables cv2x_mode for new config.
Store MAC address and Vlan id from /dev/emac to driver data.
Select right TX queue for cv2x AP and MDM mode.
Config HW register for cv2x vlan filtering.
Confgi HW register to disable checksum for CV2X queue.
Change-Id: I74b78f12e1277cddaa0fdae017f79c6b3020a36e
Acked-by: Ning Cai <ncai@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
These are custom changes to configure QMI Over ethernet and bring
up VLAN interface and queue traffic to a particular channel.
Change-Id: I83bfb74875d05eefd7ce9ab595d5e75f7d07e97d
Acked-by: Abhishek Chauhan <abchauha@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
On Link down event the rgmii clock is not setting to low speed.
Rgmii clock should change to 50Mhz when Link down event
is received.
Change-Id: I62da6683642ee5625aadc793bb8ea72e37e60b37
Signed-off-by: Karthik Rudrapatna <krudrapa@codeaurora.org>
Assigning mac addr during device boot up in emac probe function.
Change-Id: I0937354a1011ed60ee608693c3d6044d85203984
Signed-off-by: Karthik Rudrapatna <krudrapa@codeaurora.org>
Enabling RX configurations like rx_dll_bypass and rx_prog_swap
valies to be configured from device tree to support multiple
platforms.
Change-Id: I851b07563fbdf5eab9a4c15b773cacdb6b93c952
Signed-off-by: Aditya Mathur <aditmath@codeaurora.org>
Add support for all Ethernet level loopback like
IO macro, MAc, PHY . Also, Provide debugfs node for
phy off/on at suspend resume.
Change-Id: I0c095791a29120929ff52ffd77a56b1151ab9c40
Signed-off-by: Suraj Jaiswal <jsuraj@codeaurora.org>
Reset mmc counters on read to fix wrong stats in ethtool.
Change-Id: I572be9a3913f96e1feb5a845ee17a17e73be6262
Signed-off-by: Sneh Shah <snehshah@codeaurora.org>
Add check for micrel phy for phy interrupt before enabling phy irq.
Change-Id: I5f850a4c4b36373676ac3bd792eac327001a0f76
Signed-off-by: Sneh Shah <snehshah@codeaurora.org>
Don't support 1Gbps link speed when autoneg is disabled.
Change-Id: Ic40703beab56684689e686fc3e717d99be8d5bb0
Signed-off-by: Lakshit Tyagi <ltyagi@codeaurora.org>
-HWTSTAMP_FILTER_ALL with ipa enabled not supported.
-Add check for above condition to avoid crash.
Change-Id: I443122489aa257be5208bdf6260b2b3a9c8096c1
Acked-by: Ning Cai <ncai@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Use geometry mapping to optimize fastmap memory usage.
Change-Id: I0affebabeefb9b4684a27f61dc63138c0d19d864
Signed-off-by: Sneh Shah <snehshah@codeaurora.org>
Add support to read descriptor count for IPA ch from dt entry.
Change-Id: Ice9a4034275904abef374800c99b01abce44c908
Signed-off-by: Sneh Shah <snehshah@codeaurora.org>
Ported fix from 5.4:
The value of MTL_OPERATION_MODE is not written back.
Add check in ethqos to filter unsupported tx_sched_algorithm.
Signed-off-by: Cheng Han <hancheng2009@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>.
Change-Id: I329e00414e0942c542eba7ea1d3b24e450400066
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Ported fix from 5.4:
Flow control must be disabled for AVB enabled queues and TX
AVB queues must be enabled by setting BIT(2) of TXQEN.
Correct this by passing the queue mode to DMA callbacks
and by checking in these functions whether we are in AVB
performing the necessary adjustments.
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>.
Change-Id: I4daa59a97d78a427a5bb6f5f0fefb0519aad800e
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
[ Upstream commit a96ac8a0045e3cbe3e5af6d1b3c78c6c2065dec5 ]
The ipq806x_gmac_probe() function enables the PTP clock but not the
appropriate interface clocks. This means that if the bootloader hasn't
done so attempting to bring up the interface will fail with an error
like:
[ 59.028131] ipq806x-gmac-dwmac 37600000.ethernet: Failed to reset the dma
[ 59.028196] ipq806x-gmac-dwmac 37600000.ethernet eth1: stmmac_hw_setup: DMA engine initialization failed
[ 59.034056] ipq806x-gmac-dwmac 37600000.ethernet eth1: stmmac_open: Hw setup failed
This patch, a slightly cleaned up version of one posted by Sergey
Sergeev in:
https://forum.openwrt.org/t/support-for-mikrotik-rb3011uias-rm/4064/257
correctly enables the clock; we have already configured the source just
before this.
Tested on a MikroTik RB3011.
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Support reading por values for different EMAC versions.
Change-Id: I17f8e9c4d461abec29761bc96dfc1e701771de08
Acked-by: Rahul Kawadgave <rahulak@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Add support for get & set wol from the ethtool.
Also, remove duplicate message.
Change-Id: Ia7fab9706d6b67e469eac5153060cdd670c65605
Signed-off-by: Suraj Jaiswal <jsuraj@codeaurora.org>
CRC should not be stripped in SW.
Change-Id: Ie3640a6a394dd11a4d37047d789d4a02d0a560bd
Acked-by: Ning Cai <ncai@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
disable all eth clocks on suspend and enable them on resume.
Change-Id: I65e80188e2cce0967b5bce8f0f5f55c842f40aa0
Signed-off-by: Sneh Shah <snehshah@codeaurora.org>
Handle the fail case of copy from user & return
proper error.
Change-Id: I02fba52587aa91a46fd035286027510a310d23d4
Signed-off-by: Suraj Jaiswal <jsuraj@codeaurora.org>
Add packet count stats for rx and tx for each queue in ethtool.
Change-Id: I5f2c2f68fb87c9cb8436f2c589b0884404e47233
Signed-off-by: Sneh Shah <snehshah@codeaurora.org>
Port a fix from 5.4.
It forgot to reduce the value of the variable retry in a while loop
in the ethqos_configure() function. It may cause an endless loop and
without timeout.
Change-Id: Icf3887476de6bee7976eb020d18fc9f733324599
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
commit 29555fa3de865630570b5f53c847b953413daf1a upstream.
Some drivers, such as DWC EQOS on Tegra, need to perform operations that
can sleep under this lock (clk_set_rate() in tegra_eqos_fix_speed()) for
proper operation. Since there is no need for this lock to be a spinlock,
convert it to a mutex instead.
Fixes: e6ea2d16fc ("net: stmmac: dwc-qos: Add Tegra186 support")
Reported-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
When the bit is set the last four bytes of the ethernet
packet type is stripped and dropped before forwarding.
Change-Id: I740a513c90a85e3a390984602fd12539e567fc11
Acked-by: Abhishek Chauhan <abchauha@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
[ Upstream commit 91a2559c1dc5b0f7e1256d42b1508935e8eabfbf ]
In fine adjustement mode, which is the current default, the sub-second
increment register is the number of nanoseconds that will be added to
the clock when the accumulator overflows. At each clock cycle, the
value of the addend register is added to the accumulator.
Currently, we use 20ns = 1e09ns / 50MHz as this value whatever the
frequency of the ptp clock actually is.
The adjustment is then done on the addend register, only incrementing
every X clock cycles X being the ratio between 50MHz and ptp_clock_rate
(addend = 2^32 * 50MHz/ptp_clock_rate).
This causes the following issues :
- In case the frequency of the ptp clock is inferior or equal to 50MHz,
the addend value calculation will overflow and the default
addend value will be set to 0, causing the clock to not work at
all. (For instance, for ptp_clock_rate = 50MHz, addend = 2^32).
- The resolution of the timestamping clock is limited to 20ns while it
is not needed, thus limiting the accuracy of the timestamping to
20ns.
Fix this by setting sub-second increment to 2e09ns / ptp_clock_rate.
It will allow to reach the minimum possible frequency for
ptp_clk_ref, which is 5MHz for GMII 1000Mps Full-Duplex by setting the
sub-second-increment to a higher value. For instance, for 25MHz, it
gives ssinc = 80ns and default_addend = 2^31.
It will also allow to use a lower value for sub-second-increment, thus
improving the timestamping accuracy with frequencies higher than
100MHz, for instance, for 200MHz, ssinc = 10ns and default_addend =
2^31.
v1->v2:
- Remove modifications to the calculation of default addend, which broke
compatibility with clock frequencies for which 2000000000 / ptp_clk_freq
is not an integer.
- Modify description according to discussions.
Signed-off-by: Julien Beraud <julien.beraud@orolia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 15ce30609d1e88d42fb1cd948f453e6d5f188249 ]
There are 2 registers to write to enable a ptp ref clock coming from the
fpga.
One that enables the usage of the clock from the fpga for emac0 and emac1
as a ptp ref clock, and the other to allow signals from the fpga to reach
emac0 and emac1.
Currently, if the dwmac-socfpga has phymode set to PHY_INTERFACE_MODE_MII,
PHY_INTERFACE_MODE_GMII, or PHY_INTERFACE_MODE_SGMII, both registers will
be written and the ptp ref clock will be set as coming from the fpga.
Separate the 2 register writes to only enable signals from the fpga to
reach emac0 or emac1 when ptp ref clock is not coming from the fpga.
Signed-off-by: Julien Beraud <julien.beraud@orolia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Half duplex is not supported by the driver.
Return error for Half duplex setting.
Change-Id: I16bc99f66d52f236412b1513964e37f266d7c649
Signed-off-by: Suraj Jaiswal <jsuraj@codeaurora.org>
Free all allocated memory for IPA queues on closing netdev.
Change-Id: Ie6dfbd266aebef1c676028ef95af41b7c7cbed59
Signed-off-by: Sneh Shah <snehshah@codeaurora.org>
Set IOC bit for eary last segment of TSO packets.
Change-Id: I87a1b8cbd6717b0e5d32f3bd5027b935178ca39d
Acked-by: Rahul Kawadgave <rahulak@qti.qualcomm.com>
Signed-off-by: Sunil Paidimarri <hisunil@codeaurora.org>
Enable IPC logging for both high and low level.
Change-Id: I0d2ffee4a6a06df6e4968c2f1dd7e2765ea85f5e
Signed-off-by: Lakshit Tyagi <ltyagi@codeaurora.org>