PIT clock events work already and the PIT handling is the same for
i386 and x86_64. x86_64 does not support PIT as a clock source, so
disable the PIT clocksource for x86_64.
Prepare i8253.h to be shared with x8664
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Chris Wright <chrisw@sous-sol.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Add the x8664 specific bits (mapping) to share the hpet code later.
Move the reserve_platform_timer call to late init. This is necessary
for x86_64, as hpet enable() is called before memory is setup. i386
calls it in late_time_init, but it does not hurt to do it later for
both.
Pull in the x8664 hpet disable command line option as well.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
The hpet implementations of i386 and x8664 has been mostly the same
before the clock events conversion of i386. The clock events
conversion of i386 hpet is already done. So it makes sense to share
the code for the x86_64 clock events conversion.
Abstract out the mapping functions.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Chris Wright <chrisw@sous-sol.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Move the TSC calibration code to tsc.c. Reimplement it so the
pm timer can be used as a reference as well.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Chris Wright <chrisw@sous-sol.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
TSC must be verified by a continous and reliable clocksource to
allow high resolution timers and or dynamic ticks.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Add support for an MFGPT clock event device; this allows us to use MFGPTs as
the basis for high-resolution timers.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Signed-off-by: Andres Salomon <dilinger@debian.org>
Cc: Andi Kleen <ak@suse.de>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: john stultz <johnstul@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This adds support for Multi-Function General Purpose Timers. It detects the
available timers during southbridge init, and provides an API for allocating
and setting the timers. They're higher resolution than the standard PIT, so
the MFGPTs come in handy for quite a few things.
Note that we never clobber the timers that the BIOS might have opted to use;
we just check for unused timers.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Signed-off-by: Andres Salomon <dilinger@debian.org>
Cc: Andi Kleen <ak@suse.de>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Disable irq balancing on IRQ0. Several SIS chipsets lock up when you try to
change affinity of IRQ #0.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Cc: john stultz <johnstul@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
The clock events merge introduced a change to the nmi watchdog code to
handle the not longer increasing local apic timer count in the
broadcast mode. This is fine for UP, but on SMP it pampers over a
stuck CPU which is not handling the broadcast interrupt due to the
unconditional sum up of local apic timer count and irq0 count.
To cover all cases we need to keep track on which CPU irq0 is
handled. In theory this is CPU#0 due to the explicit disabling of irq
balancing for irq0, but there are systems which ignore this on the
hardware level. The per cpu irq0 accounting allows us to remove the
irq0 to CPU0 binding as well.
Add a per cpu counter for irq0 and evaluate this instead of the global
irq0 count in the nmi watchdog code.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
The next_event member of the clock event device is used to keep track
of the next periodic event. For one shot only devices it is wrong to
clear the variable, as the next event will be based on it.
Pointed out by Ralf Baechle
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Migration aid to allow preparatory patches which introduce not yet
used parts of clock events code.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
We register a simple trigger so make sure we use the corresponding
unregister function.
(Also means we get a dummy function when triggers aren't compiled in)
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
* remove pointless pci_dev_to_dev() wrapper. Just directly reference
the embedded struct device like everyone else does.
* pata_cs5520: delete cs5520_remove_one(), it was a duplicate of
ata_pci_remove_one()
* linux/libata.h: don't bother including linux/pci.h, we don't need it.
Simply declare 'struct pci_dev' and assume interested parties will
include the header, as they should be doing anyway.
* linux/libata.h: consolidate all CONFIG_PCI declarations into a
single location in the header.
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
PMP registers used to be accessed with dedicated accessors ->pmp_read
and ->pmp_write. During reset, those callbacks are called with the
port frozen so they should be able to run without depending on
interrupt delivery. To achieve this, they were implemented polling.
However, as resetting the host port makes the PMP to isolate fan-out
ports until SError.X is cleared, resetting fan-out ports while port is
frozen doesn't buy much additional safety.
This patch updates libata PMP support such that PMP registers are
accessed using regular ata_exec_internal() mechanism and kills
->pmp_read/write() callbacks. The following changes are made.
* PMP access helpers - sata_pmp_read_init_tf(), sata_pmp_read_val(),
sata_pmp_write_init_tf() are folded into sata_pmp_read/write() which
are now standalone PMP register access functions.
* sata_pmp_read/write() returns err_mask instead of rc. This is
consistent with other functions which issue internal commands and
allows more detailed error reporting.
* ahci interrupt handler is modified to ignore BAD_PMP and
spurious/illegal completion IRQs while reset is in progress. These
conditions are expected during reset.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Implement ATA_PFLAG_RESETTING. This flag is set while reset is in
progress. It's set before prereset is called and cleared after reset
fails or postreset is finished.
This flag itself doesn't have any function. It will be used by LLDs
to tell whether reset is in progress if it needs to behave differently
during reset.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Add @timeout argument to ata_exec_internal[_sg](). If 0, default
timeout ata_probe_timeout is used.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Asynchronous notification on ICH9 didn't work because it didn't write
AN FIS into the RX area - it only updates SNotification. Also,
snooping SDB_FIS RX area is racy against further SDB FIS receptions.
Let sata_async_notification() determine using SNTF if it's available
and snoop RX area iff SNTF isn't available
Signed-off-by: Tejun Heo <htejun@gmail.com>
Cc: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Now that we have pp->intr_mask, move PORT_IRQ_BAD_PMP enabling to
ahci_pmp_attach/detach() where it belongs.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
ahci had problems with NCQ over PMP and NCQ used to be disabled while
PMP was attached. After fixing the problem, the temporary NCQ
disabling code wasn't removed completely. Kill the remaining piece.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Tasks in uninterruptible sleep might be woken up by unrelated events
and should check whether the condition it was waiting for has actually
triggered. Wrap schedule_timeout_uninterruptible() in loop to achieve
it.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
ATA_EHI_NO_AUTOPSY and ATA_EHI_QUIET are used during initial probing
to skip exception analysis and reporting. Usually, there's nothing to
report but on some allowed but rare corner cases (e.g. phy status
changed interrupt when IRQ is enabled on frozen port - this happens if
IRQ pending status isn't cleared in the IRQ router or controller)
exception messages get printed.
Skip reporting if ATA_EHI_QUIET is set.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
ehi description field is used to carry LLD specific controller
description. Sometimes, it's used without clearing before and LLD
description gets printed with exception information one more time.
Clear after printing.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
PATA part of all current JMB controllers behave the same way and
JMicron confirms that all future ones will stay compatible. Drop
device matching and match only vendor and class.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Cc: Ethan Hsiao <ethanhsiao@jmicron.com>
Cc: Justin Tsai <justin@jmicron.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
On a cable there may be
eighty wires or perhaps forty
and we learn about its type
In the world of ACPI
So we call the GTM
And we find the the timing rate
And we look through it to see
If eighty wire it must be
Timing lives in ACPI routines
ACPI routines, ACPI routines
Timing lives in ACPI routines
ACPI routes ACPI routines
And the drivers last you see
Picking up unknown pci ids
and the code begins to work
Timing lives in ACPI routines
ACPI routines, ACPI routines
Timing lives in ACPI routines
ACPI routes ACPI routines
[Full speed ahead, Mr Hacker, full speed ahead]
Full speed over here sir!
Checking Cable, checking cable
Aye aye, 80 wire,
Heaven heaven]
If we use ACPI (ACPI)
Every box (every box) has all we need (has all we need)
Cable type (cable type) and mode timing (mode timing)
In our ATA (in our ATA) subroutines (subroutines, ha ha)
Timing lives in ACPI routines
ACPI routines, ACPI routines
Timing lives in ACPI routines
ACPI routes ACPI routines
Timing lives in ACPI routines
ACPI routines, ACPI routines
Timing lives in ACPI routines
ACPI routes ACPI routines
Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Talk to the dark side our driver has to, yes. Much misleading is the
data. Store it in a structure we do so that it may be parsed.
Signed-off-by: Alan Cox <alan@redhat.com>
--
Whats small, old and shouts phrases out of order across mountains ?
Yodla..
Signed-off-by: Jeff Garzik <jeff@garzik.org>
HDT722516DLA380 does spurious completion of NCQ commands. Blacklist
it.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Cc: Frans Pop <elendil@planet.nl>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Seagate Barracuda ST380817AS has troubles with NCQ. For example,
unpacking a tarball on an XFS filesystem gives this:
ata1.00: exception Emask 0x0 SAct 0x1 SErr 0x0 action 0x2 frozen
ata1.00: cmd 61/40:00:29:a3:98/00:00:00:00:00/40 tag 0 cdb 0x0 data 32768 out
res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout)
More info here:
http://lkml.org/lkml/2007/1/21/76
Blacklist it!
Signed-off-by: Paolo Ornati <ornati@fastwebnet.it>
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Some controller variants snoop the ATAPI length value for Packet
transfers to do state machine and FIFO management. Thus we want to
set it properly, even for cases where it is otherwise meaningless.
Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Correct handling of SRST reset sequences. After an SRST it is undefined
whether the drive has gone back to PIO0. In order to talk safely we should
talk slowly and carefully until we know.
Thus when we do the reset if the controller has a pio setup method we call it
to flip back to PIO 0 and a known state. After the reset completes the
identify will then be done at the safe speed and the drive/controller will
pick suitable faster modes and reconfigure the controller to these timings.
As a side effect it means we force the controller to PIO 0 as we bring it up
which fixes funnies on a few systems where the BIOS firmware leaves us in an
interesting choice of modes, or embedded boxes with no firmware which come up
in random states.
For smart controllers there is nothing to do - they know about this
internally.
Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Modern laptops with hotswap bays still tend to utilise a PATA interface
on a SATA bridge, generally with the host controller in some legacy
emulation mode rather than AHCI. This means that the existing hotplug
code in libata is unable to work. The ACPI specification states that
these devices can send notifications when hotswapped, which avoids the
need to obtain notification from the controller. This patch uses the
existing libata-acpi code and simply registers a notification in order
to trigger a rescan whenever the firmware signals an event.
Signed-off-by: Matthew Garrett <mjg59@srcf.ucam.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
This is useful when debugging, handling problem systems, or for
distributions just to get the system installed so it can be sorted
out later.
This is a bit smarter than the old IDE one and lets you do
libata.dma=0 Disable all PATA DMA like old IDE
libata.dma=1 Disk DMA only
libata.dma=2 ATAPI DMA only
libata.dma=4 CF DMA only
(or combinations thereof - 0,1,3 being the useful ones I suspect)
(I've split CF as it seems to be a seperate case of pain and suffering
different to the others and caused by assorted PIO wired adapters etc)
Signed-off-by: Alan Cox <alan@redhat.com>
[edited to work on SATA too, changing name from 'pata_dma' to 'dma']
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This adds human-readable decoding of the ATA status and error registers
(similar to what drivers/ide does) as well as the SATA Serror register
to libata error handling output. This prevents the need to pore
through standards documents to figure out the meaning of the bits
in these registers when looking at error reports. Some bits that
drivers/ide decoded are not decoded here, since the bits are either
command-dependent or obsolete, and properly parsing them would add
too much complexity.
Signed-off-by: Robert Hancock <hancockr@shaw.ca>
[edited slightly to make output a bit more symmetric]
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Of course some controllers lie about PMP support. Black list them.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Private pi.flags area is full and we need more private flags. Move
host private flags over to pi.private_data. During initialization,
these flags are copied to hpriv->flags.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Implement AHCI PMP support. ahci only supports command based
switching. Also, for some reason, NCQ over PMP doesn't work now.
Other than that, everything works.
Tested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Cc: Forrest Zhao <forrest.zhao@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
As DEV_RST (hardreset) sometimes fail to recover the controller
(especially after PMP DMA CS errata). In such cases, perform PORT_RST
prior to DEV_RST.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Implement PMP support. sil24 supports full FIS-switching. However,
it has a PMP DMA CS errata which requires port-wide resetting if
commands are outstanding to three or more devices when an error occurs
on one of them.
ATAPI commands often result in CHECK SENSE and it's crucial to not
reset them before fetching sense data. Unfortunately, ATAPI CHECK
SENSE causes a lot of problem if command is outstanding to any other
device usually resulting in port-wide reset. So, sata_sil24
implements sil24_qc_defer() which guarantees ATAPI command is run by
itself.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Extend ata_acpi_associate_sata_port() such that it can handle PMP and
call it when PMP is attached and detached.
Build breakage when !CONFIG_ATA_ACPI was spotted and fixed by Petr
Vandrovec.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Cc: Petr Vandrovec <petr@vandrovec.name>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Hook PMP support into libata and enable it. Connect SCR and probing
functions, and update ata_dev_classify() to detect PMP.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Implement Port Multiplier support. To support PMP, a LLDD has to
supply ops->pmp_read() and pmp_write(). If non-null, ->pmp_attach and
->pmp_detach are called on PMP attach and detach, respectively.
->pmp_read/write() can be called while the port is frozen, so they
must be implemented by polling. This patch supplies several helpers
to ease ->pmp_read/write() implementation.
Also, irq_handler and error_handler must be PMP aware. Most of PMP
aware EH can be done by calling ata_pmp_do_eh() with appropriate
methods. PMP EH uses separate set of reset methods and this patch
implements standard prereset, hardreset and postreset methods.
This patch only implements PMP support. The next patch will integrate
PMP into the reset of libata and thus enable PMP support.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
PMP always requires SRST to be enabled. Also, hardreset reports
classification code from the first device when PMP is attached, not
from the PMP. Update ata_eh_reset() such that followup softreset is
performed if the controller is PMP capable and the host link is being
reset.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Restore the support for handling drives that report one sector too many
(ie SCSI not ATA style). This worked before the HPA update but was
removed in that process.
Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Blacklist HITACHI HDS7250SASUN500G and HITACHI HDS7225SBSUN250G
drives using wildcard matching.
Signed-off-by David Milburn <dmilburn@redhat.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Thomas Gleixner