21b2aecaae
[MIPS] c-r3k: Implement flush_cache_range()
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Contrary to the belief of some, the R3000 and related processors did have
caches, both a data and an instruction cache. Here is an implementation
of r3k_flush_cache_page(), which is the processor-specific back-end for
flush_cache_range(), done according to the spec in
Documentation/cachetlb.txt.
While at it, remove an unused local function: get_phys_page(), do some
trivial formatting fixes and modernise debugging facilities.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
18 years ago
49a89efbbb
[MIPS] Fix "no space between function name and open parenthesis" warnings.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
18 years ago
e007566d13
[MIPS] R3000: local_flush_data_cache_page take a pointer argument.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
18 years ago
c59a0f15be
[MIPS] Remove __flush_icache_page
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__flash_icache_page is unused, so kill it.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
19 years ago
585fa72493
[MIPS] Retire flush_icache_page from mm use.
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On the 34K the redundant cache operations were causing excessive stalls
resulting in realtime code running on the second VPE missing its deadline.
For all other platforms this patch is just a significant performance
improvment as illustrated by below benchmark numbers.
Processor, Processes - times in microseconds - smaller is better
------------------------------------------------------------------------------
Host OS Mhz null null open slct sig sig fork exec sh
call I/O stat clos TCP inst hndl proc proc proc
--------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
25Kf 2.6.18-rc4 533 0.49 1.16 7.57 33.4 30.5 1.34 12.4 5497 17.K 54.K
25Kf 2.6.18-rc4-p 533 0.49 1.16 6.68 23.0 30.7 1.36 8.55 5030 16.K 48.K
4Kc 2.6.18-rc4 80 4.21 15.0 131. 289. 261. 16.5 258. 18.K 70.K 227K
4Kc 2.6.18-rc4-p 80 4.34 13.1 128. 285. 262. 18.2 258. 12.K 52.K 176K
34Kc 2.6.18-rc4 40 5.01 14.0 61.6 90.0 477. 17.9 94.7 29.K 108K 342K
34Kc 2.6.18-rc4-p 40 4.98 13.9 61.2 89.7 475. 17.6 93.7 8758 44.K 158K
BCM1480 2.6.18-rc4 700 0.28 0.60 3.68 5.92 16.0 0.78 5.08 931. 3163 15.K
BCM1480 2.6.18-rc4-p 700 0.28 0.61 3.65 5.85 16.0 0.79 5.20 395. 1464 8385
TX49-16K 2.6.18-rc3 197 0.73 2.41 19.0 37.8 82.9 2.94 17.5 4438 14.K 56.K
TX49-16K 2.6.18-rc3-p 197 0.73 2.40 19.9 36.3 82.9 2.94 23.4 2577 9103 38.K
TX49-32K 2.6.18-rc3 396 0.36 1.19 6.80 11.8 41.0 1.46 8.17 2738 8465 32.K
TX49-32K 2.6.18-rc3-p 396 0.36 1.19 6.82 10.2 41.0 1.46 8.18 1330 4638 18.K
Original patch by me with enhancements by Atsushi Nemoto.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
19 years ago
7e3bfc7cfc
[MIPS] Handle IDE PIO cache aliases on SMP.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
19 years ago
a3dddd560e
[MIPS] War on whitespace: cleanup initial spaces followed by tabs.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
19 years ago
02cf211968
Cleanup the mess in cpu_cache_init.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
20 years ago
c6e8b58771
Update MIPS to use the 4-level pagetable code thereby getting rid of
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the compacrapability headers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
20 years ago
1da177e4c3
Linux-2.6.12-rc2
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Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
20 years ago
Maciej W. Rozycki