Intel FB: allow odd- and even-field-first in interlaced modes, and
proper sync to vertical retrace
Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Cc: <sylvain.meyer@worldonline.fr>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Intel framebuffer now supports interlaced video modes.
Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
[04/05] intelfb: implement FBIO_WAITFORVSYNC ioctl
The (unofficial) FBIO_WAITFORVSYNC ioctl is implemented by sleeping on the appropriate waitqueue, as defined in my earlier patch. Currently, only display 0 (aka pipe A) is supported.
Signed-off-by: Eric Hustvedt <ehustvedt@cecropia.com>
[03/05] intelfb: Implement basic interrupt handling
Functions have been added to enable and disable interrupts using the MMIO registers. Currently only pipe A vsync interrupts are enabled.
A generalized vsync accounting struct is defined, with the intent that it can encapsulate per-pipe vsync related info in the future. Currently a single instance is hard-coded.
The interrupt service routine currently only looks for vsync interrupts on pipe A, and increments a counter and wakes up anyone waiting on it.
This implementation is heavily influenced by similar implementations in the atyfb and matroxfb drivers.
Signed-off-by: Eric Hustvedt <ehustvedt@cecropia.com>
[02/05] intelfb: Add interrupt related register definitions
Add constants for accessing HWSTAM, IER, IIR, and IMR registers.
Add constants for interrupt types supported by the 8xx and 9xx chipsets.
The registers are also stored in the hwstate struct and dumped in the debug routine.
Signed-off-by: Eric Hustvedt <ehustvedt@cecropia.com>
[01/05] intelfb: Add 16-bit register access macros
This patch adds macros to read and write two-byte MMIO registers. The interrupt-related registers are all word-sized, rather than long-sized.
Signed-off-by: Eric Hustvedt <ehustvedt@cecropia.com>
This fixes up the p calculation of p1 and p2 for the i9xx chipsets.
This seems to work a lot better for lower pixel clocks..
Signed-off-by: Dave Airlie <airlied@linux.ie>
This code just moves the PLL min/max calculations variables into
a structure, it doesn't change or add any new functionality.
Signed-off-by: Dave Airlie <airlied@linux.ie>
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Krzysztof Halasa