It still used the long-deprecated "pci_module_init()" interface, rather
than the proper "pci_register_driver()" one.
[ I don't have the hardware, and I doubt many do, but the fix is
trivial and obvious, and can't be worse than not compiling ]
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
CC fs/nfs/nfsroot.o
fs/nfs/nfsroot.c:131: error: tokens causes a section type conflict
make[2]: *** [fs/nfs/nfsroot.o] Error 1
This is due to mixing const and non-const content in the same section
which halfway recent gccs absolutely hate. Fixed by dropping the const.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* master.kernel.org:/pub/scm/linux/kernel/git/jejb/voyager-2.6:
[VOYAGER] add smp alternatives
[VOYAGER] Use modern techniques to setup and teardown low identiy mappings.
[VOYAGER] Convert the monitor thread to use the kthread API
[VOYAGER] clockevents driver: bring voyager in to line
[VOYAGER] clockevents: correct boot cpu is zero assumption
[VOYAGER] add smp_call_function_single
The S3C2410_UDC_SETIX() macro is not used and won't be used by the udc
driver, so delete it.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
linux/mmc/protocol.h header is gone, thus breaking the build of the
mach-qt2410.c file. As this header is not used, I'm removing it. The
right headers may still be added later if needed.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
And fix up the code to always allow MSI on 5714 A2.
Call tg3_find_peer() earlier because we need that information before
we can determine whether we can set TG3_FLAG_SUPPORT_MSI or not.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Without the following patch, the kernel does not automatically detect
2GB CompactFlash cards from Transcend.
Signed-off-by: Fabrice Aeschbacher <fabrice.aeschbacher@siemens.com>
Cc: Dominik Brodowski <linux@dominikbrodowski.net>
Acked-by: Peter Stuge <peter@stuge.se>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
HPT36x chip don't seem to have the channel enable bits, so prevent the IDE core
from checking them...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Michal Kepien <michal.kepien@poczta.onet.pl>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
* fix ->speedproc to set the drive speed
* this driver doesn't support SWDMA so use the correct ->swdma_mask
* BUG() if an unsupported mode is passed to ->speedproc
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This driver doesn't support SWDMA so use the correct ->swdma_mask.
While at it:
* no need to call config_chipset_for_pio() in config_chipset_for_dma(),
if DMA is not available config_chipset_for_pio() will be called
by siimage_config_drive_for_dma() and if DMA is available
config_siimage_chipset_for_pio() will be called by siimage_tune_chipset()
* remove needless config_chipset_for_pio() wrapper
* bump driver version
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
* limit max PIO mode to PIO4, this driver doesn't support PIO5 and attempt
to setup PIO5 by it821x_tuneproc() could result in incorrect PIO timings
+ incorrect base clock being set for controller in the passthrough mode
* move code limiting max PIO according to the pair device capabilities from
config_it821x_chipset_for_pio() to it821x_tuneproc() so the check is also
applied for mode change requests coming through ->tuneproc and ->speedproc
interfaces
* set device speed in it821x_tuneproc()
* in it821x_tune_chipset() call it821x_tuneproc() also if the controller is
in the smart mode (so the check for pair device max PIO is done)
* rename it821x_tuneproc() to it821x_tune_pio(), then add it821x_tuneproc()
wrapper which does the max PIO mode check; it worked by the pure luck
previously, pio[4] and pio_want[4] arrays were used with index == 255
so random PIO timings and base clock were set for the controller in the
passthrough mode, thankfully PIO timings and base clock were corrected
later by config_it821x_chipset_for_pio() call (but it was not called for
PIO-only devices during resume and for user requested PIO autotuning)
* remove config_it821x_chipset_for_pio() call from config_chipset_for_dma()
as the driver sets ->autotune to 1 and ->tuneproc does the proper job now
* convert the last user of config_it821x_chipset_for_pio() to use
it821x_tuneproc(drive, 255) and remove no longer needed function
While at it:
* fix few comments
* bump driver version
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Teach the driver's tuneproc() method to do PIO auto-runing properly since it
treated 5 instead of 255 as auto-tune request, and also passed the mode limit
of PIO5 to ide_get_best_pio_mode() despite supporting up to PIO4 only.
While at it, also:
- remove the driver's wrong claim about supporting SWDMA modes;
- stop hooking ide_dma_timeout() method as the handler clearly doesn't fit for
the task...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Fold the parts of the ide_dma_end() methods identical to __ide_dma_end() into a
mere call to it.
Start using faster versions of the ide_dma_end() and ide_dma_test_irq() methods
for the PCI0646U and newer chips that have the duplicate interrupt status bits
in the I/O mapped MRDMODE register, determing what methods to use at the driver
load time. Do some cleanup/renaming in the "old" ide_dma_test_irq() method too.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Fix several issues with the driver's procfs output:
- when testing if channel is enabled, the code looks at the "simplex" bits, not
at the real enable bits -- add #define for the primary channel enable bit;
- UltraDMA modes 0, 1, 3 for slave drive reported incorrectly due to using the
master drive's clock cycle resolution bit.
While at it, also perform the following cleanups:
- don't print extra newline before the first controller's dump;
- correct the chipset names (from CMDxxx to PCI-xxx)
- don't read from the registers which aren't used for dump;
- better align the table column sizes;
- rework UltraDMA mode dump code;
- remove PIO mode dump code that has never been finished;
- remove the duplicate interrupt status (the MRDMODE register bits mirror those
those in the CFR and ARTTIM23 registers) and fold the dump into single line;
- correct the style of the ?: operators...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
The IDE core looks at the wrong bit when checking if the secondary channel is
enabled on PCI0646 -- CNTRL register bit 7 is read-ahead disable, bit 3 is the
correct one.
Starting with PCI0646U chip, the primary channel can also be enabled/disabled --
so, add 'enablebits' initializers to each 'ide_pci_device_t' structure, handling
the original PCI0646 via adding the init_setup() method and clearing the 'reg'
field there if necessary...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
The driver's ide_dma_test_irq() method was reading the MRDMODE register even on
PCI0643/6 where it was write-only -- fix this by always reading the "backward-
compatible" interrupt bits, renaming dma_alt_stat to irq_stat as the interrupt
status bits are not coupled to DMA.
In addition, wrong interrupt bit was tested/cleared for the primary channel --
it's bit 2 in all the chip specs and the driver used bit 1... :-/
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Fix the multiword DMA and drop the single-word DMA support (which nobody will
miss, I think). In order to do it, a number of changes was necessary:
- rename program_drive_counts() to program_cycle_times(), pass to it cycle's
total/active times instead of the clock counts, and convert them into the
active/recovery clocks there instead of cmd64x_tune_pio() -- this causes
quantize_timing() to also move;
- contrarywise, move all the code handling the address setup timing into
cmd64x_tune_pio(), so that setting MWDMA mode wouldn't change address setup;
- remove from the speedproc() method the bogus code pretending to set the DMA
timings by twiddling bits in the BMIDE status register, handle setting MWDMA
by just calling program_cycle_times(); while at it, improve the style of that
whole switch statement;
- stop fiddling with the DMA capable bits in the speedproc() method -- they do
not enable DMA, and are properly dealt with by the dma_host_{on,off} methods;
- don't set hwif->swdma_mask in the init_hwif() method anymore.
In addition to those changes, do the following:
- in cmd64x_tune_pio(), when writing to ARTTIM23 register preserve the interrupt
status bit, eliminate local_irq_{save|restore}() around this code as there's
*no* actual race with the interrupt handler, and move cmdprintk() to a more
fitting place -- after ide_get_best_pio_mode() call;
- make {arttim|drwtim}_regs arrays single-dimensional, indexed with drive->dn;
- rename {setup|recovery}_counts[] into more fitting {setup|recovery}_values[];
- in the speedproc() method, get rid of the duplicate reads/writes from/to the
UDIDETCRx registers and of the extra variable used to store the transfer mode
value after filtering, use another method of determining master/slave drive,
and cleanup useless parens;
- beautify cmdprintk() output here and there.
While at it, remove meaningless comment about the driver being used only on
UltraSPARC and long non-relevant RCS tag. :-)
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Fold the now equivalent code in the ide_dma_check() method into a mere call to
ide_use_dma(). Make config_for_dma() return non-zero if DMA mode has been set
and call it from the ide_dma_check() method instead of ide_dma_on().
Defer writing the DMA timings to the chip registers until DMA is really turned
on (and do not enable IORDY for DMA).
Remove unneeded code from the init_hwif() method, improve its overall looks.
Rename the dma_start(), ide_dma_check(), and ide_dma_lostirq() methods, and
also use more proper hwif->dma_command, fix printk() and comment in the latter
one as well. While at it, cleanup style in several places.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Get rid of the 'pio_speed' member of 'ide_drive_t' that was only used by this
driver by storing the PIO mode timings in the 'drive_data' instead -- this
allows us to greatly simplify the process of "reloading" of the chip's timing
register and do it right in sl82c150_dma_off_quietly() and to get rid of two
extra arguments to config_for_pio() -- which got renamed to sl82c105_tune_pio()
and now returns a PIO mode selected, with ide_config_drive_speed() call moved
into the tuneproc() method, now called sl82c105_tune_drive() with the code to
set drive's 'io_32bit' and 'unmask' flags in its turn moved to its proper place
in the init_hwif() method.
Also, while at it, rename get_timing_sl82c105() into get_pio_timings() and get
rid of the code in it clamping cycle counts to 32 which was both incorrect and
never executed anyway...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
__ioremap() took a set of page table flags (specifically the cacheable
and bufferable bits) to control the mapping type. However, with
the advent of ARMv6, this is far too limited.
Replace the page table flags with a memory type index, so that the
desired attributes can be selected from the mem_type table.
Finally, to prevent silent miscompilation due to the differing
arguments, rename the __ioremap() and __ioremap_pfn() functions.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch removes the use of the TG3_FLAG_5701_REG_WRITE_BUG flag.
It's logic is only used to set a function pointer and thus the
logic can be collapsed and the flag removed.
[ Comment tidy by Christoph Hellwig. -DaveM ]
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Add cached device type for ioremap_cached(). Group all device memory
types together, and ensure that they all have a "MT_DEVICE" prefix.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The reset was added a while back so that ASF could re-init whatever
MAC address it wanted to use after the MAC address was changed.
Instead of resetting, we can just keep MAC address 1 unchanged during
MAC address changes if MAC address 1 is different from MAC address 0.
This fixes 2 problems:
1. Bonding calls set_mac_address in contexts that cannot sleep.
It no longer sleeps with the chip reset removed.
2. When ASF shares the same MAC address as the NIC, it needs to
always do that even when the MAC address is changed.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Change the memory types table to define the L1 descriptor bit 4 to
be in terms of the ARMv6 definition - execute never.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Change TG3_FLAG_SERDES_WOL_CAP to TG3_FLAG_WOL_CAP to make it easier
to manage WoL. This flag is now used consistently during ethtool WoL
setup and power setting changes.
Signed-off-by: Gary Zambrano <zambrano@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The GPIO settings may change during reset and so the stored values in
tp->grc_local_ctrl should be cleared first.
Signed-off-by: Gary Zambrano <zambrano@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch changes the NVRAM sizing procedure so that the driver can
take advantage of devices with 1:1 NVRAM strapping configurations. This
is useful in cases where the traditional NVRAM sizing method fails. In
the event that the flash size cannot be determined, the largest known
NVRAM size is used. The patch also removes support for 5755 NVRAM
devices that are not supported by Broadcom and adds explicit sizing for
this device.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
1. Remove the check for skb->len greater than MTU when doing TSO.
When the destination has a smaller MSS than the source, a TSO packet
may be smaller than the MTU and we still need to process it as a TSO
packet.
2. On 5705A3 devices with TSO enabled, the DMA engine can hang due to a
hardware bug. This patch avoids the hanging condition by reducing the
DMA burst size.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add MAINTAINERS entry for mac80211.
Signed-off-by: Jiri Benc <jbenc@suse.cz>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Export various mac80211 internal variables through debugfs.
Signed-off-by: Jiri Benc <jbenc@suse.cz>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add generic IEEE 802.11 definitions.
Signed-off-by: Jiri Benc <jbenc@suse.cz>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
People treating the *_pid fields in netlink as a process ID has caused
endless confusion over the years. The fact that our own netlink.h
does this only adds to the confusion.
So here is a patch to change the comments to refer to it as the port
ID which hopefully will make it clear what the purpose of the fields
really is.
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
From: Heiko Carstens <heiko.carstens@de.ibm.com>
CC [M] net/iucv/af_iucv.o
net/iucv/af_iucv.c: In function `iucv_fragment_skb':
net/iucv/af_iucv.c:984: error: structure has no member named `h'
net/iucv/af_iucv.c:985: error: structure has no member named `nh'
net/iucv/af_iucv.c:988: error: incompatible type for argument 1 of
`skb_queue_tail'
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Fix:
drivers/serial/8250.c:1837: warning: suggest parentheses around arithmetic in operand of |
due to a macro argument being used without required parenthesis.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix oops in omap16xx mpuio suspend/resume code; field wasn't initialized
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
GPIO and MPUIO wake updates:
- Hook MPUIOs into the irq wakeup framework too. This uses a platform
device to update irq enables during system sleep states, instead of
a sys_device, since the latter is no longer needed for such things.
- Also forward enable/disable irq wake requests to the relevant GPIO
controller, so the top level IRQ dispatcher can (eventually) handle
these wakeup events automatically if more than one GPIO pin needs to
be a wakeup event source.
- Minor tweak to the 24xx non-wakeup gpio stuff: no need to check such
read-only data under the spinlock.
This assumes (maybe wrongly?) that only 16xx can do GPIO wakeup; without
a 15xx I can't test such stuff.
Also this expects the top level IRQ dispatcher to properly handle requests
to enable/disable irq wake, which is currently known to be wrong: omap1
saves the flags but ignores them, omap2 doesn't even save it. (Wakeup
events are, wrongly, hardwired in the relevant mach-omapX/pm.c file ...)
So MPUIO irqs won't yet trigger system wakeup.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Speedup and shrink GPIO irq handling code, by using a pointer
that's available in the irq_chip structure instead of calling
the get_gpio_bank() function. On OMAP1 this saves 44 words,
most of which were in IRQ critical path methods. Hey, every
few instructions help.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds minimal OMAP2430 support to plat-omap files to
get the kernel booting on 2430SDP.
Signed-off-by: Syed Mohammed Khasim <x0khasim@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
More GPIO/IRQ cleanup:
- compile-time removal of much useless code
* mpuio support on non-OMAP1.
* 15xx/730/24xx gpio support on 1610
* 15xx/730/16xx gpio support on 24xx
* etc
- remove all BUG() calls, which are always bad news ... replaced some
with normal fault reports for that call, others with WARN_ON(1).
- small mpuio bugfix: add missing set_type() method
Oh, and fix a minor merge issue: inode->u.generic_ip is now gone.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add some GPIO debug support: /sys/kernel/debug/omap_gpio dumps the state
of all GPIOs that have been claimed, including basic IRQ info if relevant.
Tested on 24xx, 16xx.
Includes minor bugfixes: recording IRQ trigger mode (this should probably
be a genirq patch), adding missing space to non-wakeup warning
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Some GPIOs on OMAP2420 do not have wakeup capabilities. If these GPIOs
are configured as IRQ sources, spurious interrupts will be generated
each time the core domain enters retention.
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Enable 24xx GPIO autoidling
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds support for the D-Link DSM-G600 Rev A.
This is an ARM XScale IXP4xx system relatively similar to
the NSLU2 and NAS-100D already supported by mainline. An
important difference is Gigabit Ethernet support using
the Via Velocity chipset.
This patch is the combined work of Michael Westerhof and
Alessandro Zummo, with contributions from Michael-Luke
Jones. This version addresses review comments from rmk
and Deepak Saxena.
Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk>
Signed-off-by: Alessandro Zummo <a.zummo@towertech.it>
Signed-off-by: Michael Westerhof <mwester@dls.net>
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Linus Torvalds