kernel_samsung_sm7125

jenna

Commit Graph

Author	SHA1	Message	Date
Dale Farnsworth	e44b894190	[POWERPC] Add interrupt support for Marvell mv64x60 chips There are 3 interrupt groups each with its own status/mask registers. We use a separate struct irq_chip for each interrupt group and handle interrupts in two stages or levels: level 1 selects the appropriate struct irq_chip, and level 2 selects individual interrupts within that irq_chip. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Paul Mackerras <paulus@samba.org>	18 years ago

Author

SHA1

Message

Date

Dale Farnsworth

e44b894190

[POWERPC] Add interrupt support for Marvell mv64x60 chips

There are 3 interrupt groups each with its own status/mask registers.
We use a separate struct irq_chip for each interrupt group and handle
interrupts in two stages or levels: level 1 selects the appropriate
struct irq_chip, and level 2 selects individual interrupts within
that irq_chip.

Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

18 years ago

1 Commits (58ea1aa07e3cb4674ab0261b45aa1ba68282a79d)