Presently this is uninitialized in the architecture code, so it's
artificlally capped to the default initialization value. Set it up at
registration time.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The PMCAT location has conveniently moved on newer SH-X3 parts, special
case this for now with a note. This will probably want to be redone in a
less visually offensive way when/if more information becomes available.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Checks for (irq < 0) and (ilsel < 0) didn't make sense since they were
unsigned. Made them signed.
Signed-off-by: Vasiliy Kulikov <segooon@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
SH-3 lacks an MMUCR_TI definition for global TLB flushes. As SH-3 parts
lack a split TLB, the same global flush behaviour is accomplished
through the flush bit, which just happens to be the same as on SH-4.
This fixes up the build for all SH-3 MMU parts.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The spinlock in traps_64.c is used without initialization.
This fixes it by declaring DEFINE_SPINLOCK() and makes the spinlock static
variable.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: linux-sh@vger.kernel.org
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
SH7786 is the big user for subgroup splitting, mostly for the PCIe block,
but those will follow later. For now we simply split up SCIF1, as used by
the serial console on SDK7786 and others.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Many interrupts that share a single mask source but are on different
hardware vectors will have an associated register tied to an INTEVT that
denotes the precise cause for the interrupt exception being triggered.
This introduces the concept of IRQ subgroups in the intc core, where
a virtual IRQ map is constructed for each of the pre-defined cause bits,
and a higher level chained handler takes control of the parent INTEVT.
This enables CPUs with heavily muxed IRQ vectors (especially across
disjoint blocks) to break things out in to a series of managed chained
handlers while being able to dynamically lookup and adopt the IRQs
created for them.
This is largely an opt-in interface, requiring CPUs to manually submit
IRQs for subgroup splitting, in addition to providing identifiers in
their enum maps that can be used for lazy lookup via the radix tree.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
At the moment ILSEL blows up with a BUG when aliased sets are handed in,
but as the enable call is able to hand back errors we opt for that path
instead. None of the ILSEL peripherals are vital to the board's
operation, so trapping a BUG is a bit excessive.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds gpio-keys mappings for the button matrix on the baseboard,
now that we have support for the pin controller.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds trivial support for the GPIOs implemented through the baseboard
CPLD, used for driving the button matrix.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
As non-PFC chips are added that may support IRQs, pass through to the
generic helper instead of triggering the WARN_ON().
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Some controllers will need to be initialized lazily due to pinmux
constraints, while others may simply have no need to be brought online if
there are no backing devices for them attached. In this case it's still
necessary to be able to reserve their hardware vector map before dynamic
IRQs get a hold of them.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The SH-X3 proto CPU has all of the external IRQ and IRL pins muxed, make
sure that we're able to grab them before attempting to register their
respective IRQ controllers.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds in support for GPIO/pinmux on the SH-X3 proto CPUs. This will
subsequently be used by the x3proto board.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds in hardware IRQ auto-distribution support for SH-X3 proto CPUs,
following the SH7786 support.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This shuffles some of the shared bits out of the 7786 code and in to a
shared SH-X3 support file. Presently just for userimask, but also a good
place for the IRQ balancing wrappers.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Update the SH kernel to keep SR.BL set until the VBR
register has been initialized. Useful to allow boot
of the kernel even though exceptions are pending.
Without this patch there is a window of time when
exceptions such as NMI are enabled but no exception
handlers are installed.
This patch modifies both the zImage loader and the
actual kernel to boot with BL=1, but the zImage
loader is modfied in such a way that the init_sr
value is unchanged to not break the zImage loader
provided by kexec.
Tested on sh7724 Ecovec and on the SH4AL-DSP core
included in sh7372.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
kfree() in clkdev_drop() function should actually be called with an address of
a struct clk_lookup_alloc object, and not struct clk_lookup, as presently done.
This just happens to work, because "struct clk_lookup cl" is the first
member in struct clk_lookup_alloc.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
While sh previously had its own debugfs root, there now exists a
common arch_debugfs_dir prototype, so we switch everything over to
that. Presumably once more architectures start making use of this
we'll be able to just kill off the stub kdebugfs wrapper.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This copies the pci_config_lock idea from x86 over, allowing us to kill
off a couple of existing private locks. At the same time, these need to
be converted to raw spinlocks for -rt kernels, so we make that change at
the same time. This should make it easier for future parts to get the
locking right instead of inevitable ending up with lock type mismatches.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This gets each port handling its MSTP bit, as well as moving the PHY
clock management in to the clock framework.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Some of the existing code is flipping between __raw_xxx() and
pci_{read,write}_reg(). As the latter are just wrappers for the former,
flip over to using them consistently.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Presently we error out if a link is disabled and simply drop the port
registration outright. This follows the PPC changes and simply reports on
the link state on boot, leaving the port registered, in order to more
easily deal with hotplug on future parts.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
These settings are properly propagated by the hardware already, so
there's no need to bother with them manually.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The SH7786 PCIe is presently unable to enumerate itself in root complex
mode, and has no visibility through either type 0 or type 1 accesses,
despite having a mostly sensible extended config space for each port.
Attempts to generate type 0 or type 1 config cycles result in completer
aborts, so we're ultimately forced to use SuperHyway transactions
instead.
As each port has a single port <-> device mapping that resolves for any
PCI_SLOT definition, we simply hijack devfn 0 for the SuperHyway
transaction and bump up the devfn limit.
With enumeration of the root complex now possible, we also need to insert
an early fixup to hide the BARs from the kernel. With all of that done,
it's now possible to use the pcieport services with all of the PCIe
ports, which is the first step to power management support.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Previously these IDs were only used by one driver, so there was not much
need for having them generically defined. Now that this will no longer
hold true, move them over.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The spec suggests waiting up to 500ms for the PHY to settle before
testing link state, but practice shows that 100ms is sufficient (this is
the delay value we also use on the other SH-4A PCI controllers, too).
This makes device detection much more reliable, although in the future it
should be a bit faster to simply serialize with a TLP IRQ.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The only BKL user in arch/sh protects a single bit,
so we can trivially replace it with test_and_set_bit.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: linux-sh@vger.kernel.org
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Now that the rest of the socket calls are provided through their own
paths, do the same for sys_recvmmsg. It's unlikely we'll ever be able to
kill off the socketcall path, but this at least permits userspace to
gradually begin migrating.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Linux kernel already has socket syscalls that can be invoked
without the multiplexing sys_socketcall wrapper.
C library wrappers are ready to use them directly. It needs just
to define the missing syscall numbers and provide the related entries
into the syscalls table, like sh64 aleady does.
Signed-off-by: Francesco Rundo <francesco.rundo@st.com>
Signed-off-by: Carmelo Amoroso <carmelo.amoroso@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch modify x_plate_ohms to correct value for tsc2007 panel,
and removed un-necessary ts_get_pendown_state()
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
As the help for the config option suggests, this option really shouldn't
be set by default for any recent distribution as it changes the layout
of sysfs. I spotted this while running debian when udev got very
confused by the sysfs layout and failed to create some device nodes.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Now that the resource assignment issues are resolved, we can finally wire
up the small third memory window -- in the future we may reclaim this for
MSI.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
An IORESOURCE_IO was missing here, which meant that we weren't properly
establishing the I/O window for this particular slot. With this
corrected, cards with I/O BARs have them actually assigned and
accessible.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Certain memory windows are only available for 32-bit space, so skip over
these in 29-bit mode. This will severely restrict the amount of memory
that can be mapped, but since a boot loader bug makes booting in 29-bit
mode close to impossible anyways, everything is ok.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This bumps up the low address to match the physical memory windows for
SHway<->PCIe transfers. The previous implementation was banking on a 1:1
virt<->phys SHway mapping, which doesn't apply here.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
SH7786 PCIe has 1 slot per port, but no specific restriction on function.
Relax the devfn restriction and look to the slot number instead when
configured as a root complex.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This brings the clocking and register setting in line with the somewhat
factually ambiguous specification.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Paul Mundt