Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
[Modified to hit the right file]
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Dynamically detect the DBx500 SOC an revision based on the ASIC ID.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Rename the MOP board Kconfig entries to the same name as the machine
type, so that the machine_is_*() macros work correctly.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
[Updated to match changes in the tree]
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
To allow the possiblity of building U8500 and U5500 support in the same
image.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
[Rebased to latest changes in Russells tree]
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Suffix the U5500 modem IRQ and MBOX files with *-db5500* so that
we clearly know the SoC they belong to, in line with the rest of
the files in mach-ux500.
Cc: Stefan Nilsson <stefan.xk.nilsson@stericsson.com>
Cc: Martin Persson <martin.persson@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
There is a subtle race in the CPU hotplug code, where a CPU which has
been offlined can online itself before being requested, which results
in things going astray on the next online/offline cycle.
What happens in the normal online/offline/online cycle is:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads -1
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
However, as the write of -1 of pen_release is not fully flushed back to
memory, and the checking of pen_release is done with caches disabled,
this allows CPU3 the opportunity to read the old value of pen_release:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads 3
starts boot
pen_release = -1
requests boot of CPU3
pen_release = 3
flush cache line
Fix this by grouping the write of pen_release along with its cache line
flushing code to ensure that any update to pen_release is always pushed
out to physical memory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
With "ARM: CPU hotplug: remove bug checks in platform_cpu_die()", we
now do not use hard_smp_processor_id(), we no longer need to read the
hardware processor ID. Remove the include providing this function.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
platform_cpu_die() is entered from the CPU's own idle thread, which
can not be migrated to other CPUs. Moreover, the 'cpu' argument
comes from the thread info, which will always be the 'current'
CPU. So remove this useless bug check.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
We always need to wait for the dying CPU to reach a safe state before
taking it down, irrespective of the requirements of the platform.
Move the completion code into the ARM SMP hotplug code rather than
having each platform re-implement this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
All platforms call trace_hardirqs_off() in their secondary startup code,
so move this into the core SMP code - it doesn't need to be in the
per-platform code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There is a certain amount of smp_prepare_cpus() which doesn't belong
in the platform support code - that is, code which is invariant to the
SMP implementation. Move this code into arch/arm/kernel/smp.c, and
add a platform_ prefix to the original function.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
scu_get_core_count() never returns zero cores, so we don't need to
check and correct if ncores is zero.
Tegra was missing the check against NR_CPUS, leading to a potential
bitfield overflow if this becomes the case.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Ensure that the number of CPUs is sanity checked before setting
the number of possible CPUs. This avoids any chance of overflowing
the cpu_possible bitmap.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move keylayouts to a dedicated file and plug these keylayouts
for input platform data. This will make addition of new and custom
keylayouts localized.
Signed-off-by: Sundar Iyer <sundar.iyer@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Add block identifier to be able to add multiple mfd clients
to the mfd core
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Sundar Iyer <sundar.iyer@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Most of the register layout, client IRQ numbers on the TC35892 is shared also
by other variants. Make this generic as tc3589x
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Sundar Iyer <sundar.iyer@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Provide a standard get_irqnr_preamble assembler macro for platforms
to use, which retrieves the base address of the GIC CPU interface
from gic_cpu_base_addr. Allow platforms to override this by defining
HAVE_GET_IRQNR_PREAMBLE.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
We don't need to re-pass the base address for the CPU interfaces to the
GIC for secondary CPUs, as it will never be different from the boot CPU
- and even if it was, we'd overwrite the boot CPU's base address.
Get rid of this argument, and rename to gic_secondary_init().
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Provide gic_init() which initializes the GIC distributor and current
CPU's GIC interface for the boot (or single) CPU.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Adds support in PRCMU driver to handle CPU and APE operating points.
Signed-off-by: Martin Persson <martin.persson@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
The DB5500 PER6 clock rate is the same as the DB8500 one, i.e. 133.33 MHz.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Remove the irq number macros which don't specify which SoC they're for.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
The uncompress code for zImage uses the UART to print status messages,
this was hard coded to use UART2 for the U8500 platform. This patch
checks at run time which platform it is run on. U5500 uses UART0 as
console UART.
Signed-off-by: Carl-Johan Irekvist <carl-johan.irekvist@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Add basic DMA configuration for u5500 supporting memcpy.
Make way for SDI0 dma support by setting SDI0 to -1,
indicating it will be configured in runtime.
Signed-off-by: Per Forlin <per.forlin@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
U5500 now boots from sdi0 (onboard eMMC).
Change machine type to U5500.
Adjust uart and sdi0 clock rates for u5500.
All necessary clocks must be enabled before Linux starts because
there is no clock tree support in u5500 yet.
Signed-off-by: Per Forlin <per.forlin@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
PRCMU driver only supports u8500. Don't
initialize prcmu if running on u5500.
Signed-off-by: Per Forlin <per.forlin@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
PRCM_TCR enables the various timers in the system. This must be achieved
before any of the MTUs are usable for kernel usage. Explicit enabling of
this in the kernel makes it independent of bootloader actions.
Signed-off-by: Sundar Iyer <sundar.iyer@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
This patch removes the dublicated define for number of
interrupts and instead include the needed header file.
Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
This patch adds support for db8500 chip version 2.
The TCDM memory address of the PRCMU is changed and
dynamic detection of that is added.
Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Change the Ux500 devices to be dynamically allocated and added by
calling functions instead of referencing structures, thereby allowing
5500 and other derivatives' support to be added without having to
duplicate structures, use fixup functions, or use compile-time macros.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Use the GIC demux code in asm/hardware/entry-macro-gic.S
on the UX500 subarchitecture.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This allows us to use smp_cross_call() to trigger a number of different
software generated interrupts, rather than combining them all on one
SGI. Recover the SGI number via do_IPI.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
factorise some generic infrastructure to assist looking up struct clks
for the ARM & SH architecture.
as the code is identical at 99%
put the arch specific code for allocation as example in asm/clkdev.h
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This change updates the ux500 specific outer cache code to use
the new *_relaxed() I/O accessors.
Signed-off-by: Per Fransson <per.xx.fransson@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The generic version of l2x0_inv_all is only called just after disabling
the L2 cache and is surrounded by a spinlock. However, we're not really
turning off the L2 cache right now, and the PL310 does not support
exclusive accesses (used to implement the spinlock). So, the
invalidation needs to be done without the spinlock.
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Hans-Juergen Koch <hjk@linutronix.de>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Per Fransson <per.xx.fransson@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Since we're now using addruart to establish the debug mapping, we can
remove the io_pg_offst and phys_io members of struct machine_desc.
The various declarations were removed using the following script:
grep -rl MACHINE_START arch/arm | xargs \
sed -i '/MACHINE_START/,/MACHINE_END/ { /\.\(phys_io\|io_pg_offst\)/d }'
[ Initial patch was from Jeremy Kerr, example script from Russell King ]
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Eric Miao <eric.miao at canonical.com>
Rabin Vincent