Long ago in the dark ages this was used a MIPS a.out binary to be used
with Milo which is obsolete since years.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
With some memory model other than FLATMEM, the single node can
contains some holes so there might be many invalid pages. For
example, with two 256M memory and one 256M hole, some variables
(num_physpage, totalpages, nr_kernel_pages, nr_all_pages, etc.) will
indicate that there are 768MB on this system. This is not desired
because, for example, alloc_large_system_hash() allocates too many
entries.
Use free_area_init_node() with counted zholes_size[] instead of
free_area_init().
For num_physpages, use number of ram pages instead of max_low_pfn.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1. MIPS should select SPARSEMEM_STATIC since allocating bootmem in
memory_present() will corrupt bootmap area.
2. pfn_valid() for SPARSEMEM is defined in linux/mmzone.h
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
this patch restores the behaviour of the old (assembly-written)
interrupt handler, the handler is left as soon as a single interrupt
cause is handled.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The appended patch drops the inline for decode_configs, this saves about
2k of text size.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This might be helpfull to debug sparsemem on mips.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This might be helpfull to debug sparsemem on mips.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Make the MT handler silent and output the MT exception type at debug
priority.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This fixes the "not syncing: Could not identify cpu/level ..." panic
when a PCI irq is requested the second time.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
On the 34K where multiple virtual processors are implemented in a single
core and share a single TLB, interprocessor function calls are not needed
to flush a cache, so avoid them.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Since this assignment was the only place on !alpha where isa_bridge was
touched, it didn't have any effect.
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There is an implicit assumption in the code that ranges will translate
to something that can fit in 2 32-bit cells, or a 64-bit value. For
certain kinds of things below PCI this isn't necessarily true.
Here is what the relevant OF device hierarchy looks like for one of
the serial controllers on an Ultra5:
Node 0xf005f1e0
ranges: 00000000.00000000.00000000.000001fe.01000000.00000000.01000000
01000000.00000000.00000000.000001fe.02000000.00000000.01000000
02000000.00000000.00000000.000001ff.00000000.00000001.00000000
03000000.00000000.00000000.000001ff.00000000.00000001.00000000
device_type: 'pci'
model: 'SUNW,sabre'
Node 0xf005f9d4
device_type: 'pci'
model: 'SUNW,simba'
Node 0xf0060d24
ranges: 00000010.00000000 82010810.00000000.f0000000 01000000
00000014.00000000 82010814.00000000.f1000000 00800000
name: 'ebus'
Node 0xf0062dac
reg: 00000014.003083f8.00000008 --> 0x1ff.f13083f8
device_type: 'serial'
name: 'su'
So the correct translation here is:
1) Match "su" register to second ranges entry of 'ebus', which translates
into a PCI triplet "82010814.00000000.f1000000" of size 00800000, which
gives us "82010814.00000000.f13083f8".
2) Pass-through "SUNW,simba" since it lacks ranges property
3) Match "82010814.00000000.f13083f8" to third ranges property of PCI
controller node 'SUNW,sabre', and we arrive at the final physical
MMIO address of "0x1fff13083f8".
Due to the 2-cell assumption, we couldn't translate to a PCI 3-cell
value, and we couldn't perform a pass-thru on it either.
It was easiest to just stop splitting the ranges application operation
between two methods, ->map and ->translate, and just let ->map do all
the work. That way it would work purely on 32-bit cell arrays instead
of having to "return" some value like a u64.
It's still not %100 correct because the out-of-range check is still
done using the 64 least significant bits of the range and address.
But it does work for all the cases I've thrown at it so far.
Signed-off-by: David S. Miller <davem@davemloft.net>
It is only needed when there is a PCI-PCI bridge sitting
between the device and the PCI host controller which is
not a Simba APB bridge.
Add logic to handle two special cases:
1) device behind EBUS, which sits on PCI
2) PCI controller interrupts
Signed-off-by: David S. Miller <davem@davemloft.net>
When installing the IRQ pre-handler, we were not setting up the second
argument correctly. It should be a pointer to the sabre_irq_data, not
the config space PIO address.
Furthermore, we only need this pre-handler installed if the device
sits behind a PCI bridge that is not Sabre or Simba/APB.
Signed-off-by: David S. Miller <davem@davemloft.net>
device_create_file() can fail. This causes the sparc64 compile to
fail when my fanatical __must_check patch is applied, due to -Werror.
[ Added necessary identical fix for sparc32. -DaveM]
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch adds a proper prototype for pcibios_sort() in
arch/i386/pci/pci.h.
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
1. Multipath devices for which SetPGID is not supported are not handled well.
Use NOP ccws for path verification (sans path grouping) when SetPGID is not
supported.
2. Check for PGIDs already set with SensePGID on _all_ paths (not just the
first one) and try to find a common one. Moan if no common PGID can be
found (and use NOP verification). If no PGIDs have been set, use the css
global PGID (as before). (Rationale: SetPGID will get a command reject if
the PGID it tries to set does not match the already set PGID.)
3. Immediately before reboot, issue RESET CHANNEL PATH (rcp) on all chpids. This
will remove the old PGIDs. rcp will generate solicited CRWs which can be
savely ignored by the machine check handler (all other actions create
unsolicited CRWs).
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Patch from Pavel Machek
Also warn users about charging in unsuitable temperature.
Signed-off-by: Pavel Machek <pavel@suse.cz>
Acked-by: Richard Purdie <rpurdie@rpsys.net>
Acked-by: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Patch from Pavel Machek
It seems that sharp had charger on by default... This at least turns
it off. Also battery reading now works and is useful.
Signed-off-by: Pavel Machek <pavel@suse.cz>
Acked-by: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Patch from Thomas Gleixner
From: Thomas Gleixner <tglx@linutronix.de>
The genirq conversion of ARM lost a CPU Hotplug helper function.
Restore it.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Patch from Pavel Machek
From: Dirk Opfer <Dirk@Opfer-Online.de>
Fix ucb initialization on collie. Wrong frequency was used and that
led to things not working quite correctly. (I had to actually disable
checks in my tree to get it to boot). It now includes all the
neccessary parts to get it to compile :-).
Signed-off-by: Pavel Machek <pavel@suse.cz>
Acked-by: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
If a configuration was chosen to support both the Versatile
AB and PB boards, the result would write to registers not
available on the PB version of the board. Resolve this by
using machine_is_xxx().
Also, for the CLCD, despite how the code looks, both the AB
and PB access the same location to control the clock rate -
it's just called something different between the two board
versions. Invent our own name for this location and use it
unconditionally.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
We can't safely directly access an compat_alloc_user_space() pointer
with the siginfo copy functions. Bounce it through the stack.
Noticed by Al Viro using sparse
[ This was only added post 2.6.17, not in any released kernel ]
Cc: Al Viro <viro@ftp.linux.org.uk>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Add it for P4 model 6 - reported to work and have a similar PMU to
earlier P4s.
Add an p4force=1 module override parameter for future use.
We had a discussion about that earlier - it's a trade off between the
PMU staying compatible or not. I think the force parameter is a
reasonable compromise.
Cc: oprofile-list@lists.sf.net
Cc: Asit Mallick <asit.k.mallick@intel.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Ralf Baechle