1 Commits (1d4de9edd6c9ad676b20729ab15c04b78e9a50c5)

Author	SHA1	Message	Date
Dale Farnsworth	e44b894190	[POWERPC] Add interrupt support for Marvell mv64x60 chips ... There are 3 interrupt groups each with its own status/mask registers. We use a separate struct irq_chip for each interrupt group and handle interrupts in two stages or levels: level 1 selects the appropriate struct irq_chip, and level 2 selects individual interrupts within that irq_chip. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Paul Mackerras <paulus@samba.org>	18 years ago