2 Commits (0aa97d6e420039fc4a6040acdf53e56e0f90c0f5)

Author	SHA1	Message	Date
Dale Farnsworth	e1a3107b06	[POWERPC] Add Marvell mv64x60 PCI bridge support ... This patch adds PCI bridge support for the Marvell mv64x60 chip. We also provide the ability to read/write the mv64x60 hotswap register via sysfs if the hs_reg_valid property is set in the device tree. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>	18 years ago
Dale Farnsworth	e44b894190	[POWERPC] Add interrupt support for Marvell mv64x60 chips ... There are 3 interrupt groups each with its own status/mask registers. We use a separate struct irq_chip for each interrupt group and handle interrupts in two stages or levels: level 1 selects the appropriate struct irq_chip, and level 2 selects individual interrupts within that irq_chip. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Paul Mackerras <paulus@samba.org>	18 years ago