Convert all GIC DT initialization over to use common irqchip_init
function.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Now that we have drivers/irqchip, move GIC irqchip to drivers/irqchip. This
is necessary to share the GIC with arm and arm64.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Now that the GIC initialization sets up the handle_arch_irq pointer, we
can remove it for all machines and make it static.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Anton Vorontsov <avorontsov@mvista.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Set handle_arch_irq to gic_handle_irq. Only the first GIC initialized can
setup the handler.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Olof Johansson <olof@lixom.net>
In preparation of moving gic code to drivers/irqchip, remove the direct
platform dependencies on gic_raise_softirq. Move the setup of
smp_cross_call into the gic code and use arch_send_wakeup_ipi_mask
function to trigger wake-up IPIs.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
With multi irq handler and all GIC users converted to it, we don't need
asm/hardware/gic.h to be included in assembly. Clean-up ifdefs and
unnecessary includes.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Olof Johansson <olof@lixom.net>
The commit 7d28e3eaa1
("ARM: ux500: wake secondary cpu via resched") makes use
of schedule IPI to wake up the secondary core which seems
incorrect. Rather use SGI0.
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Olof Johansson <olof@lixom.net>
In order to allow irqchip drivers to register their IRQ handling
function as the parent IRQ controller handler function, we provide a
convenience function. This will avoid poking directly into the global
handle_arch_irq variable.
Suggested by Arnd Bergmann.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
[Rob Herring: remove warning. 1st one to initialize wins.]
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Olof Johansson <olof@lixom.net>
I mismerged a previous branch from Alexander, and accidentally left
in ARCH_USES_GETTIMEOFFSET. Remove it.
Signed-off-by: Olof Johansson <olof@lixom.net>
Cc: Alexander Shiyan <shc_work@mail.ru>
This fixes suspend to RAM adding necessary save and restore of L2 and GIC.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
When we fail to power down, we need to clear out the power request.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
With commit 384a290 (ARM: gic: use a private mapping for CPU target
interfaces), wake-up IPIs now go to all cores as the gic cpu interface
numbering may not follow core numbering. This broke secondary boot on
highbank since the boot address was already set for all secondary cores,
this caused all cores to boot before the kernel was ready.
Fix this by moving the setting of the jump address to
highbank_boot_secondary instead of highbank_smp_prepare_cpus and
highbank_cpu_die. Also, clear the address when we boot. This prevents
cores from booting before they are actually triggered and is also necessary
to get suspend/resume to work.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
With the addition of commit a0ae0240 (ARM: kernel: add device tree init
map function), the cpu reg values must match the cpu mpidr register or we'll
get warnings. For some reason, the CLUSTERID on highbank is 9, so the reg
value needs to be 0x90n to quiet the warnings.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
While device_type is considered deprecated, it is still needed for tools
like lshw to identify cpu nodes.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The second FlexCAN port uses different clock than the first one, configure
correct clock to prevent hanging of the system during bringing up of the port.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The IRQ array must be terminated by -1 and not by -1+OMAP_INTC_START
This led to having a resource list of 100s of IRQs.
Looks like this was caused by commit a2cfc509 (ARM: OMAP3+: hwmod: Add
AM33XX HWMOD data) that probably had some search and replace updates
done for the patch for sparse irq support.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
[tony@atomide.com: updated wit information about the breaking commit]
Signed-off-by: Tony Lindgren <tony@atomide.com>
During merge of the mvebu patches a clock gate for pinctrl was
lost. This patch just readds the clock gate.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The use of writel instead of writel_relaxed lead to deadlock in some
situation (SMP on Armada 370 for instance). The use of writel_relaxed
as it was done in the rest of this driver fixes this bug.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch fixes a bug for Aurora L2 cache controller when the
write-through mode is enable. For the clean operation even if we don't
have to flush the lines we still need to invalidate them.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
If CONFIG_ARCH_MULTIPLATFORM & CONFIG_ARCH_MVEBU are both enabled,
__v7_pj4b_setup is added between __v7_ca9mp_setup and __v7_setup.
But there's no jump instruction added. If the chip is Cortex A5/A9,
it goes through __v7_pj4b_setup also. It results in system hang.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since commit 62e4d357a (ARM: 7609/1: disable errata work-arounds which access
secure registers) ARM_ERRATA_743622/751472 depends on !ARCH_MULTIPLATFORM.
Since imx has been converted to multiplatform, the following warning happens:
$ make imx_v6_v7_defconfig
warning: (SOC_IMX6Q && ARCH_TEGRA_2x_SOC && ARCH_TEGRA_3x_SOC) selects
ARM_ERRATA_751472 which has unmet direct dependencies (CPU_V7 &&
!ARCH_MULTIPLATFORM)
warning: (SOC_IMX6Q && ARCH_TEGRA_3x_SOC) selects ARM_ERRATA_743622
which has unmet direct dependencies (CPU_V7 && !ARCH_MULTIPLATFORM)
warning: (SOC_IMX6Q && ARCH_TEGRA_3x_SOC) selects ARM_ERRATA_743622
which has unmet direct dependencies (CPU_V7 && !ARCH_MULTIPLATFORM)
warning: (SOC_IMX6Q && ARCH_TEGRA_2x_SOC && ARCH_TEGRA_3x_SOC) selects
ARM_ERRATA_751472 which has unmet direct dependencies (CPU_V7 &&
!ARCH_MULTIPLATFORM)
Recommended approach is to remove ARM_ERRATA_743622/751472 from being selected
by SOC_IMX6Q and apply such workarounds into the bootloader.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The Armada XP MV78230 DT include file is missing a ; at the
end of the cpu node.
Reported-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
We originally thought that the MV78230 variant of the Armada XP had
four Ethernet interfaces, like the other variants MV78260 and
MV78460. In fact, this is not true, and the MV78230 has only three
Ethernet interfaces.
So, the definitions of the Ethernet interfaces is now done as follows:
* armada-370-xp.dtsi: definitions of the first two interfaces, that
are common to Armada 370 and Armada XP
* armada-xp.dtsi: definition of the third interface, common to all
Armada XP variants.
* armada-xp-mv78260.dtsi and armada-xp-mv78460.dtsi: definition of
the fourth interface.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Contrary to our understanding at the time armada-xp-mv78230.dtsi was
written, the MV78230 variant of the Armada XP SoC has two cores and
not one. This patch updates the .dtsi file to take into account this
reality.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
With the change to a DT based pinctrl/gpio driver, using gpio API
calls in board-*.c files no longer works, a dereferenced NULL pointer
exception occurs instead. By converting the GPIO code into a
fixed-regulator which gets probed later once pinctrl/gpio is
available, we avoid the exception.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Stefan Peter <s.peter@mplch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
We moved to declaring clk gates in DT. However, device which do not
yet have a DT binding need to have a clkdev alias. This was missing
for SDIO.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Stefan Peter <s.peter@mplch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Clock Management of kirkwood has moved to DT clock providers.
However, TWSI1 has not yet been done.
This switches TWSI1 of 88f6282 to DT clock providers.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Without the clock being held by a driver, it gets turned off at a bad
time causing the SoC to lockup. This is often during reboot.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Stefan Peter <s.peter@mpl.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The UART controller used in the Armada 370 and Armada XP SoCs is the
Synopsys DesignWare 8250 (aka Synopsys DesignWare ABP UART). The
improper use of the ns16550 can lead to a kernel oops during boot if
a character is sent to the UART before the initialization of the
driver. The DW APB has an extra interrupt that gets raised when
writing to the LCR when busy. This explains why we need to use
dw-apb-uart driver to handle this.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Since exynos5440 can support only common clk stuff, so this
patch skips legacy exynos5 clock initialization.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
In the compatible field we should point the manufacturer of the board, which
in this case is Buglabs.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
CONFIG_HOTPLUG is going away as an option. As a result, the __dev*
markings need to be removed.
This change removes the use of __devinit, __devexit_p, __devinitdata,
and __devexit from these drivers.
Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.
Cc: Bill Pemberton <wfp5p@virginia.edu>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Bump the IRQ numbers from offset at 1 (right above NO_IRQ)
to 32. This is the painful way to learn that if you're using
SPARSE_IRQ and avoid to define .nr_irqs in your machine,
the first 16 IRQs will be pre-allocated, and the IRQdomain
code (as the VIC core code before it) will then assume
that all IRQ descriptors are pre-allocated, and 16 of them
are - by somebody else. So mapping the IRQs will fail in
irq_create_mapping(). Moving the offset upward rids us of
this problem.
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This reference to the old include header for the FSMC NAND
MTD driver was somehow left in place, get rid of it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On OMAP2xxx chips, the register bitfields for the
PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED are
different than those used on OMAP3/4. The order is reversed. So, for
example, on OMAP2xxx, 0x0 indicates 'ON'; but on OMAP3/4, 0x0
indicates 'OFF'. Similarly, on OMAP2xxx, 0x3 indicates 'OFF', but on
OMAP3/4, 0x3 indicates 'ON'.
To fix this, we treat the OMAP3/4 values as the powerdomain API
values, and create new low-level powerdomain functions for the
OMAP2xxx chips which translate between the OMAP2xxx values and the
OMAP3/4 values.
Without this patch, the conversion of the OMAP2xxx PM code to the
functional powerstate code results in a non-booting kernel.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The ETM/ETB drivers for OMAP3, enable the emu_src_ck clock in order
to access the ETM/ETB hardware. The emu_src_ck should enable the EMU
clock domain so that the ETM/ETB hardware is accessible. However,
currently when enabling the emu_src_ck the EMU clock domain is not
being enabled and so the ETM/ETB drivers are failing. Add enable/disable
clock functions to enable the EMU clock domain when enabling the
emu_src_ck.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
To read reset sources registers we have to use PRM_DEVICE_INST
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
RSTTIME is offset 0x8 and RSTST is offset 0x04 for OMAP4430 and
OMAP4460.
Signed-off-by: Nishanth Menon <nm@ti.com>
[ivan.khoronzhuk@ti.com: ported from k3.4]
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
In the map for reset sources register we use defines intended for
using with PRM_RSTCTRL register. So fix it.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add DT support for twl4030_wdt. This is needed to get twl4030_wdt to
probe when booting with DT.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
The VIC irqdomain code added in commit
07c9249f1f
"ARM: 7554/1: VIC: use irq_domain_add_simple()"
Had two bugs:
1) It didn't call irq_create_mapping() once on each
valid irq source in the slowpath when registering
the controller.
2) It passed a -1 as IRQ offset for the DT case, whereas
0 should be passed as invalid IRQ instead.
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The Versatile starts to register Linux IRQ numbers from offset 0
which is illegal, since this is NO_IRQ. Bump all hard-coded IRQs
by 32 to get rid of the problem.
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
In order to support secure and non-secure platforms in multi-platform
kernels, errata work-arounds that access secure only registers need to
be disabled. Make all the errata options that fit in this category
depend on !CONFIG_ARCH_MULTIPLATFORM.
This will effectively remove the errata options as platforms are
converted over to multi-platform.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
PL310 errata work-arounds using .set_debug function are only needed on
r3p0 and earlier, so check the rev and only set .set_debug on older revs.
Avoiding debug register accesses fixes aborts on non-secure platforms
like highbank. It is assumed that non-secure platforms needing these
work-arounds have already implemented .set_debug with secure monitor
calls.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Commit bb77209432 ("ARM: OMAP: Move
omap2+ specific parts of sram.c to mach-omap2") adds some new sparse
warnings:
arch/arm/plat-omap/sram.c:43:6: warning: symbol 'omap_sram_push_address' was not declared. Should it be static?
arch/arm/plat-omap/sram.c:65:6: warning: symbol 'omap_sram_reset' was not declared. Should it be static?
arch/arm/plat-omap/sram.c:73:13: warning: symbol 'omap_map_sram' was not declared. Should it be static?
This second version fixes the warnings by including <plat/sram.h>, at
Tony's request.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Commit 70384a6af0 ("ARM: OMAP3+:
hwmod: Add AM33XX HWMOD data for davinci_mdio module") adds two
new sparse warnings:
arch/arm/mach-omap2/omap_hwmod_33xx_data.c:2518:30: warning: symbol 'am33xx_mdio_addr_space' was not declared. Should it be static?
arch/arm/mach-omap2/omap_hwmod_33xx_data.c:2526:26: warning: symbol 'am33xx_cpgmac0__mdio' was not declared. Should it be static?
Fix by marking the two new records as static.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Peter Korsgaard <jacmet@sunsite.dk>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: David S. Miller <davem@davemloft.net>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
This patch removes following warning in kernel boot log,
Because EXYNOS5440 can support only Pinctrl not GPIO.
WARNING: at drivers/gpio/gpio-samsung.c:3102 samsung_gpiolib_init+0x68/0x8c()
Unknown SoC in gpio-samsung, no GPIOs added
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Rob Herring