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ARM: dts: msm: Add eMMC, SD card support on sdm429w

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Add eMMC and SD card support on SDM429w.

Change-Id: Id8e2d348a337ae4b2d0287cc4383327cdcd1474a
Signed-off-by: Sridhar Arra <sarra@codeaurora.org>
tirimbino
Sridhar Arra 5 years ago
parent 4a4761eafd
commit ff856260ce
6 changed files with 409 additions and 2 deletions
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  1. 41
      arch/arm64/boot/dts/qcom/sda429-wdp.dtsi
  2. 41
      arch/arm64/boot/dts/qcom/sda429-wtp.dtsi
  3. 152
      arch/arm64/boot/dts/qcom/sdm429-pinctrl.dtsi
  4. 41
      arch/arm64/boot/dts/qcom/sdm429-wdp.dtsi
  5. 41
      arch/arm64/boot/dts/qcom/sdm429-wtp.dtsi
  6. 95
      arch/arm64/boot/dts/qcom/sdm429.dtsi

41
arch/arm64/boot/dts/qcom/sda429-wdp.dtsi
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@ -11,3 +11,44 @@
* GNU General Public License for more details.
*/
&sdhc_1 {
/* device core power supply */
vdd-supply = <&L19A>;
qcom,vdd-voltage-level = <2900000 3200000>;
qcom,vdd-current-level = <200 570000>;
/* device communication power supply */
vdd-io-supply = <&L13A>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 60000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
status = "ok";
};
&sdhc_2 {
/* device core power supply for sd card*/
vdd-supply = <&vreg_sd_vdd>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <15000 800000>;
/* device communication power supply for msm_io*/
vdd-io-supply = <&vreg_sd_pad>;
qcom,vdd-io-voltage-level = <1800000 2950000>;
qcom,vdd-io-current-level = <200 22000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&tlmm 67 0x1>;
status = "disabled";
};

41
arch/arm64/boot/dts/qcom/sda429-wtp.dtsi
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@ -11,3 +11,44 @@
* GNU General Public License for more details.
*/
&sdhc_1 {
/* device core power supply */
vdd-supply = <&L19A>;
qcom,vdd-voltage-level = <2900000 3200000>;
qcom,vdd-current-level = <200 570000>;
/* device communication power supply */
vdd-io-supply = <&L13A>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 60000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
status = "ok";
};
&sdhc_2 {
/* device core power supply for sd card*/
vdd-supply = <&vreg_sd_vdd>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <15000 800000>;
/* device communication power supply for msm_io*/
vdd-io-supply = <&vreg_sd_pad>;
qcom,vdd-io-voltage-level = <1800000 2950000>;
qcom,vdd-io-current-level = <200 22000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&tlmm 67 0x1>;
status = "disabled";
};

152
arch/arm64/boot/dts/qcom/sdm429-pinctrl.dtsi
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@ -625,5 +625,157 @@
};
};
};
pmx_sdc1_rclk {
sdc1_rclk_on: sdc1_rclk_on {
config {
pins = "sdc1_rclk";
bias-pull-down; /* pull down */
};
};
sdc1_rclk_off: sdc1_rclk_off {
config {
pins = "sdc1_rclk";
bias-pull-down; /* pull down */
};
};
};
pmx_sdc1_clk {
sdc1_clk_on: sdc1_clk_on {
config {
pins = "sdc1_clk";
bias-disable; /* NO pull */
drive-strength = <16>; /* 16 MA */
};
};
sdc1_clk_off: sdc1_clk_off {
config {
pins = "sdc1_clk";
bias-disable; /* NO pull */
drive-strength = <2>; /* 2 MA */
};
};
};
pmx_sdc1_cmd {
sdc1_cmd_on: sdc1_cmd_on {
config {
pins = "sdc1_cmd";
bias-pull-up; /* pull up */
drive-strength = <10>; /* 10 MA */
};
};
sdc1_cmd_off: sdc1_cmd_off {
config {
pins = "sdc1_cmd";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
};
pmx_sdc1_data {
sdc1_data_on: sdc1_data_on {
config {
pins = "sdc1_data";
bias-pull-up; /* pull up */
drive-strength = <10>; /* 10 MA */
};
};
sdc1_data_off: sdc1_data_off {
config {
pins = "sdc1_data";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
};
sdhc2_cd_pin {
sdc2_cd_on: cd_on {
mux {
pins = "gpio67";
function = "gpio";
};
config {
pins = "gpio67";
drive-strength = <2>;
bias-pull-up;
};
};
sdc2_cd_off: cd_off {
mux {
pins = "gpio67";
function = "gpio";
};
config {
pins = "gpio67";
drive-strength = <2>;
bias-disable;
};
};
};
pmx_sdc2_clk {
sdc2_clk_on: sdc2_clk_on {
config {
pins = "sdc2_clk";
drive-strength = <16>; /* 16 MA */
bias-disable; /* NO pull */
};
};
sdc2_clk_off: sdc2_clk_off {
config {
pins = "sdc2_clk";
bias-disable; /* NO pull */
drive-strength = <2>; /* 2 MA */
};
};
};
pmx_sdc2_cmd {
sdc2_cmd_on: sdc2_cmd_on {
config {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_cmd_off: sdc2_cmd_off {
config {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
};
pmx_sdc2_data {
sdc2_data_on: sdc2_data_on {
config {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_data_off: sdc2_data_off {
config {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
};
};
};

41
arch/arm64/boot/dts/qcom/sdm429-wdp.dtsi
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@ -11,3 +11,44 @@
* GNU General Public License for more details.
*/
&sdhc_1 {
/* device core power supply */
vdd-supply = <&L19A>;
qcom,vdd-voltage-level = <2900000 3200000>;
qcom,vdd-current-level = <200 570000>;
/* device communication power supply */
vdd-io-supply = <&L13A>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 60000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
status = "ok";
};
&sdhc_2 {
/* device core power supply for sd card*/
vdd-supply = <&vreg_sd_vdd>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <15000 800000>;
/* device communication power supply for msm_io*/
vdd-io-supply = <&vreg_sd_pad>;
qcom,vdd-io-voltage-level = <1800000 2950000>;
qcom,vdd-io-current-level = <200 22000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&tlmm 67 0x1>;
status = "disabled";
};

41
arch/arm64/boot/dts/qcom/sdm429-wtp.dtsi
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@ -11,3 +11,44 @@
* GNU General Public License for more details.
*/
&sdhc_1 {
/* device core power supply */
vdd-supply = <&L19A>;
qcom,vdd-voltage-level = <2900000 3200000>;
qcom,vdd-current-level = <200 570000>;
/* device communication power supply */
vdd-io-supply = <&L13A>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 60000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
status = "ok";
};
&sdhc_2 {
/* device core power supply for sd card*/
vdd-supply = <&vreg_sd_vdd>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <15000 800000>;
/* device communication power supply for msm_io*/
vdd-io-supply = <&vreg_sd_pad>;
qcom,vdd-io-voltage-level = <1800000 2950000>;
qcom,vdd-io-current-level = <200 22000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&tlmm 67 0x1>;
status = "disabled";
};

95
arch/arm64/boot/dts/qcom/sdm429.dtsi
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@ -123,8 +123,10 @@
};
aliases { };
aliases {
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
sdhc2 = &sdhc_2; /* SDC2 for SD card */
};
soc: soc { };
@ -301,6 +303,95 @@
status = "disabled";
};
sdhc_1: sdhci@7824900 {
compatible = "qcom,sdhci-msm";
reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>;
reg-names = "hc_mem", "core_mem", "cmdq_mem";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,bus-width = <8>;
qcom,large-address-bus;
qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
192000000 384000000>;
qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,msm-bus,name = "sdhc1";
qcom,msm-bus,num-cases = <9>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
<78 512 1046 3200>, /* 400 KB/s*/
<78 512 52286 160000>, /* 20 MB/s */
<78 512 65360 200000>, /* 25 MB/s */
<78 512 130718 400000>, /* 50 MB/s */
<78 512 130718 400000>, /* 100 MB/s */
<78 512 261438 800000>, /* 200 MB/s */
<78 512 261438 800000>, /* 400 MB/s */
<78 512 1338562 4096000>; /* Max. bandwidth */
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000
50000000 100000000 200000000 400000000 4294967295>;
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "iface_clk", "core_clk", "ice_core_clk";
qcom,scaling-lower-bus-speed-mode = "DDR52";
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040874>;
qcom,nonremovable;
status = "disabled";
};
sdhc_2: sdhci@7864900 {
compatible = "qcom,sdhci-msm";
reg = <0x7864900 0x500>, <0x7864000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,bus-width = <4>;
qcom,large-address-bus;
qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
200000000>;
qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
"SDR104";
qcom,msm-bus,name = "sdhc2";
qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
<81 512 1046 3200>, /* 400 KB/s*/
<81 512 52286 160000>, /* 20 MB/s */
<81 512 65360 200000>, /* 25 MB/s */
<81 512 130718 400000>, /* 50 MB/s */
<81 512 261438 800000>, /* 100 MB/s */
<81 512 261438 800000>, /* 200 MB/s */
<81 512 1338562 4096000>; /* Max. bandwidth */
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
100000000 200000000 4294967295>;
qcom,devfreq,freq-table = <50000000 200000000>;
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface_clk", "core_clk";
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040874>;
status = "disabled";
};
qcom,msm-imem@8600000 {
compatible = "qcom,msm-imem";
reg = <0x08600000 0x1000>; /* Address and size of IMEM */

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