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@ -969,15 +969,11 @@ int __init init_arch_irq(void) |
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#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) |
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bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); |
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bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); |
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bfin_write_SIC_IWR0(IWR_ENABLE_ALL); |
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bfin_write_SIC_IWR1(IWR_ENABLE_ALL); |
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# ifdef CONFIG_BF54x |
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bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); |
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bfin_write_SIC_IWR2(IWR_ENABLE_ALL); |
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# endif |
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#else |
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bfin_write_SIC_IMASK(SIC_UNMASK_ALL); |
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bfin_write_SIC_IWR(IWR_ENABLE_ALL); |
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#endif |
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SSYNC(); |
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@ -1106,6 +1102,16 @@ int __init init_arch_irq(void) |
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IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
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IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
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#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) |
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bfin_write_SIC_IWR0(IWR_ENABLE_ALL); |
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bfin_write_SIC_IWR1(IWR_ENABLE_ALL); |
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# ifdef CONFIG_BF54x |
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bfin_write_SIC_IWR2(IWR_ENABLE_ALL); |
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# endif |
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#else |
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bfin_write_SIC_IWR(IWR_ENABLE_ALL); |
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#endif |
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return 0; |
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} |
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