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@ -235,47 +235,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, |
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return 0; |
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} |
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int |
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nouveau_channel_idle(struct nouveau_channel *chan) |
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{ |
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struct drm_device *dev = chan->dev; |
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struct drm_nouveau_private *dev_priv = dev->dev_private; |
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struct nouveau_engine *engine = &dev_priv->engine; |
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uint32_t caches; |
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int idle; |
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if (!chan) { |
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NV_ERROR(dev, "no channel...\n"); |
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return 1; |
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} |
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caches = nv_rd32(dev, NV03_PFIFO_CACHES); |
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nv_wr32(dev, NV03_PFIFO_CACHES, caches & ~1); |
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if (engine->fifo.channel_id(dev) != chan->id) { |
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struct nouveau_gpuobj *ramfc = |
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chan->ramfc ? chan->ramfc->gpuobj : NULL; |
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if (!ramfc) { |
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NV_ERROR(dev, "No RAMFC for channel %d\n", chan->id); |
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return 1; |
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} |
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engine->instmem.prepare_access(dev, false); |
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if (nv_ro32(dev, ramfc, 0) != nv_ro32(dev, ramfc, 1)) |
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idle = 0; |
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else |
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idle = 1; |
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engine->instmem.finish_access(dev); |
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} else { |
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idle = (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET) == |
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nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT)); |
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} |
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nv_wr32(dev, NV03_PFIFO_CACHES, caches); |
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return idle; |
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} |
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/* stops a fifo */ |
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void |
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nouveau_channel_free(struct nouveau_channel *chan) |
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