This commit implements the base CPU clocks for sunxi devices. It has
been tested using a slightly modified cpufreq driver from the
linux-sunxi 3.0 tree.
Additionally, document the new bindings introduced by this patch.
Idling:
/ # cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
osc32k 0 0 32768
osc24M_fixed 0 0 24000000
osc24M 0 0 24000000
apb1_mux 0 0 24000000
apb1 0 0 24000000
pll1 0 0 60000000
cpu 0 0 60000000
axi 0 0 60000000
ahb 0 0 60000000
apb0 0 0 30000000
dummy 0 0 0
After "yes >/dev/null &":
/ # cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
osc32k 0 0 32768
osc24M_fixed 0 0 24000000
osc24M 0 0 24000000
apb1_mux 0 0 24000000
apb1 0 0 24000000
pll1 0 0 1008000000
cpu 0 0 1008000000
axi 0 0 336000000
ahb 0 0 168000000
apb0 0 0 84000000
dummy 0 0 0
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
tirimbino
Emilio López
12 years ago
committed by
Mike Turquette
parent
b548916851
commit
e874a66977
@ -0,0 +1,44 @@ |
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Device Tree Clock bindings for arch-sunxi |
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This binding uses the common clock binding[1]. |
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
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Required properties: |
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- compatible : shall be one of the following: |
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"allwinner,sunxi-osc-clk" - for a gatable oscillator |
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"allwinner,sunxi-pll1-clk" - for the main PLL clock |
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"allwinner,sunxi-cpu-clk" - for the CPU multiplexer clock |
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"allwinner,sunxi-axi-clk" - for the sunxi AXI clock |
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"allwinner,sunxi-ahb-clk" - for the sunxi AHB clock |
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"allwinner,sunxi-apb0-clk" - for the sunxi APB0 clock |
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"allwinner,sunxi-apb1-clk" - for the sunxi APB1 clock |
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"allwinner,sunxi-apb1-mux-clk" - for the sunxi APB1 clock muxing |
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Required properties for all clocks: |
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- reg : shall be the control register address for the clock. |
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- clocks : shall be the input parent clock(s) phandle for the clock |
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- #clock-cells : from common clock binding; shall be set to 0. |
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For example: |
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osc24M: osc24M@01c20050 { |
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#clock-cells = <0>; |
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compatible = "allwinner,sunxi-osc-clk"; |
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reg = <0x01c20050 0x4>; |
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clocks = <&osc24M_fixed>; |
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}; |
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pll1: pll1@01c20000 { |
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#clock-cells = <0>; |
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compatible = "allwinner,sunxi-pll1-clk"; |
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reg = <0x01c20000 0x4>; |
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clocks = <&osc24M>; |
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}; |
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cpu: cpu@01c20054 { |
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#clock-cells = <0>; |
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compatible = "allwinner,sunxi-cpu-clk"; |
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reg = <0x01c20054 0x4>; |
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clocks = <&osc32k>, <&osc24M>, <&pll1>; |
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}; |
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@ -0,0 +1,5 @@ |
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#
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# Makefile for sunxi specific clk
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#
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obj-y += clk-sunxi.o clk-factors.o
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@ -0,0 +1,180 @@ |
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/*
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* Copyright (C) 2013 Emilio López <emilio@elopez.com.ar> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* Adjustable factor-based clock implementation |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/module.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/err.h> |
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#include <linux/string.h> |
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#include <linux/delay.h> |
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#include "clk-factors.h" |
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/*
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* DOC: basic adjustable factor-based clock that cannot gate |
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* |
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* Traits of this clock: |
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* prepare - clk_prepare only ensures that parents are prepared |
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* enable - clk_enable only ensures that parents are enabled |
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* rate - rate is adjustable. |
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* clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1) |
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* parent - fixed parent. No clk_set_parent support |
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*/ |
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struct clk_factors { |
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struct clk_hw hw; |
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void __iomem *reg; |
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struct clk_factors_config *config; |
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void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p); |
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spinlock_t *lock; |
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}; |
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#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) |
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#define SETMASK(len, pos) (((-1U) >> (31-len)) << (pos)) |
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#define CLRMASK(len, pos) (~(SETMASK(len, pos))) |
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#define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit)) |
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#define FACTOR_SET(bit, len, reg, val) \ |
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(((reg) & CLRMASK(len, bit)) | (val << (bit))) |
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static unsigned long clk_factors_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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u8 n = 1, k = 0, p = 0, m = 0; |
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u32 reg; |
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unsigned long rate; |
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struct clk_factors *factors = to_clk_factors(hw); |
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struct clk_factors_config *config = factors->config; |
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/* Fetch the register value */ |
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reg = readl(factors->reg); |
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/* Get each individual factor if applicable */ |
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if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE) |
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n = FACTOR_GET(config->nshift, config->nwidth, reg); |
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if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE) |
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k = FACTOR_GET(config->kshift, config->kwidth, reg); |
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if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE) |
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m = FACTOR_GET(config->mshift, config->mwidth, reg); |
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if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE) |
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p = FACTOR_GET(config->pshift, config->pwidth, reg); |
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/* Calculate the rate */ |
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rate = (parent_rate * n * (k + 1) >> p) / (m + 1); |
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return rate; |
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} |
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static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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struct clk_factors *factors = to_clk_factors(hw); |
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factors->get_factors((u32 *)&rate, (u32)*parent_rate, |
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NULL, NULL, NULL, NULL); |
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return rate; |
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} |
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static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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u8 n, k, m, p; |
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u32 reg; |
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struct clk_factors *factors = to_clk_factors(hw); |
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struct clk_factors_config *config = factors->config; |
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unsigned long flags = 0; |
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factors->get_factors((u32 *)&rate, (u32)parent_rate, &n, &k, &m, &p); |
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if (factors->lock) |
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spin_lock_irqsave(factors->lock, flags); |
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/* Fetch the register value */ |
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reg = readl(factors->reg); |
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/* Set up the new factors - macros do not do anything if width is 0 */ |
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reg = FACTOR_SET(config->nshift, config->nwidth, reg, n); |
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reg = FACTOR_SET(config->kshift, config->kwidth, reg, k); |
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reg = FACTOR_SET(config->mshift, config->mwidth, reg, m); |
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reg = FACTOR_SET(config->pshift, config->pwidth, reg, p); |
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/* Apply them now */ |
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writel(reg, factors->reg); |
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/* delay 500us so pll stabilizes */ |
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__delay((rate >> 20) * 500 / 2); |
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if (factors->lock) |
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spin_unlock_irqrestore(factors->lock, flags); |
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return 0; |
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} |
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static const struct clk_ops clk_factors_ops = { |
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.recalc_rate = clk_factors_recalc_rate, |
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.round_rate = clk_factors_round_rate, |
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.set_rate = clk_factors_set_rate, |
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}; |
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/**
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* clk_register_factors - register a factors clock with |
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* the clock framework |
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* @dev: device registering this clock |
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* @name: name of this clock |
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* @parent_name: name of clock's parent |
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* @flags: framework-specific flags |
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* @reg: register address to adjust factors |
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* @config: shift and width of factors n, k, m and p |
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* @get_factors: function to calculate the factors for a given frequency |
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* @lock: shared register lock for this clock |
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*/ |
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struct clk *clk_register_factors(struct device *dev, const char *name, |
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const char *parent_name, |
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unsigned long flags, void __iomem *reg, |
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struct clk_factors_config *config, |
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void (*get_factors)(u32 *rate, u32 parent, |
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u8 *n, u8 *k, u8 *m, u8 *p), |
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spinlock_t *lock) |
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{ |
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struct clk_factors *factors; |
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struct clk *clk; |
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struct clk_init_data init; |
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/* allocate the factors */ |
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factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL); |
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if (!factors) { |
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pr_err("%s: could not allocate factors clk\n", __func__); |
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return ERR_PTR(-ENOMEM); |
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} |
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init.name = name; |
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init.ops = &clk_factors_ops; |
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init.flags = flags; |
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init.parent_names = (parent_name ? &parent_name : NULL); |
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init.num_parents = (parent_name ? 1 : 0); |
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/* struct clk_factors assignments */ |
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factors->reg = reg; |
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factors->config = config; |
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factors->lock = lock; |
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factors->hw.init = &init; |
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factors->get_factors = get_factors; |
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/* register the clock */ |
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clk = clk_register(dev, &factors->hw); |
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if (IS_ERR(clk)) |
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kfree(factors); |
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return clk; |
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} |
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@ -0,0 +1,27 @@ |
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#ifndef __MACH_SUNXI_CLK_FACTORS_H |
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#define __MACH_SUNXI_CLK_FACTORS_H |
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#include <linux/clk-provider.h> |
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#include <linux/clkdev.h> |
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#define SUNXI_FACTORS_NOT_APPLICABLE (0) |
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struct clk_factors_config { |
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u8 nshift; |
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u8 nwidth; |
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u8 kshift; |
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u8 kwidth; |
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u8 mshift; |
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u8 mwidth; |
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u8 pshift; |
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u8 pwidth; |
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}; |
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struct clk *clk_register_factors(struct device *dev, const char *name, |
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const char *parent_name, |
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unsigned long flags, void __iomem *reg, |
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struct clk_factors_config *config, |
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void (*get_factors) (u32 *rate, u32 parent_rate, |
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u8 *n, u8 *k, u8 *m, u8 *p), |
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spinlock_t *lock); |
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#endif |
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@ -0,0 +1,362 @@ |
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/*
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* Copyright 2013 Emilio López |
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* |
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* Emilio López <emilio@elopez.com.ar> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/clkdev.h> |
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#include <linux/clk/sunxi.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include "clk-factors.h" |
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static DEFINE_SPINLOCK(clk_lock); |
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/**
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* sunxi_osc_clk_setup() - Setup function for gatable oscillator |
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*/ |
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#define SUNXI_OSC24M_GATE 0 |
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static void __init sunxi_osc_clk_setup(struct device_node *node) |
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{ |
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struct clk *clk; |
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const char *clk_name = node->name; |
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const char *parent; |
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void *reg; |
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reg = of_iomap(node, 0); |
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parent = of_clk_get_parent_name(node, 0); |
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clk = clk_register_gate(NULL, clk_name, parent, CLK_IGNORE_UNUSED, |
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reg, SUNXI_OSC24M_GATE, 0, &clk_lock); |
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if (clk) { |
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of_clk_add_provider(node, of_clk_src_simple_get, clk); |
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clk_register_clkdev(clk, clk_name, NULL); |
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} |
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} |
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/**
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* sunxi_get_pll1_factors() - calculates n, k, m, p factors for PLL1 |
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* PLL1 rate is calculated as follows |
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* rate = (parent_rate * n * (k + 1) >> p) / (m + 1); |
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* parent_rate is always 24Mhz |
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*/ |
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static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate, |
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u8 *n, u8 *k, u8 *m, u8 *p) |
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{ |
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u8 div; |
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/* Normalize value to a 6M multiple */ |
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div = *freq / 6000000; |
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*freq = 6000000 * div; |
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/* we were called to round the frequency, we can now return */ |
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if (n == NULL) |
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return; |
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/* m is always zero for pll1 */ |
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*m = 0; |
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/* k is 1 only on these cases */ |
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if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000) |
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*k = 1; |
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else |
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*k = 0; |
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/* p will be 3 for divs under 10 */ |
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if (div < 10) |
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*p = 3; |
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/* p will be 2 for divs between 10 - 20 and odd divs under 32 */ |
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else if (div < 20 || (div < 32 && (div & 1))) |
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*p = 2; |
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/* p will be 1 for even divs under 32, divs under 40 and odd pairs
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* of divs between 40-62 */ |
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else if (div < 40 || (div < 64 && (div & 2))) |
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*p = 1; |
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/* any other entries have p = 0 */ |
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else |
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*p = 0; |
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/* calculate a suitable n based on k and p */ |
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div <<= *p; |
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div /= (*k + 1); |
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*n = div / 4; |
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} |
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/**
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* sunxi_get_apb1_factors() - calculates m, p factors for APB1 |
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* APB1 rate is calculated as follows |
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* rate = (parent_rate >> p) / (m + 1); |
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*/ |
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static void sunxi_get_apb1_factors(u32 *freq, u32 parent_rate, |
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u8 *n, u8 *k, u8 *m, u8 *p) |
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{ |
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u8 calcm, calcp; |
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if (parent_rate < *freq) |
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*freq = parent_rate; |
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parent_rate = (parent_rate + (*freq - 1)) / *freq; |
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/* Invalid rate! */ |
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if (parent_rate > 32) |
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return; |
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if (parent_rate <= 4) |
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calcp = 0; |
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else if (parent_rate <= 8) |
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calcp = 1; |
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else if (parent_rate <= 16) |
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calcp = 2; |
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else |
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calcp = 3; |
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calcm = (parent_rate >> calcp) - 1; |
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*freq = (parent_rate >> calcp) / (calcm + 1); |
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/* we were called to round the frequency, we can now return */ |
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if (n == NULL) |
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return; |
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*m = calcm; |
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*p = calcp; |
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} |
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/**
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* sunxi_factors_clk_setup() - Setup function for factor clocks |
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*/ |
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struct factors_data { |
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struct clk_factors_config *table; |
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void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); |
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}; |
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static struct clk_factors_config pll1_config = { |
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.nshift = 8, |
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.nwidth = 5, |
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.kshift = 4, |
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.kwidth = 2, |
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.mshift = 0, |
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.mwidth = 2, |
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.pshift = 16, |
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.pwidth = 2, |
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}; |
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static struct clk_factors_config apb1_config = { |
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.mshift = 0, |
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.mwidth = 5, |
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.pshift = 16, |
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.pwidth = 2, |
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}; |
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static const __initconst struct factors_data pll1_data = { |
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.table = &pll1_config, |
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.getter = sunxi_get_pll1_factors, |
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}; |
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static const __initconst struct factors_data apb1_data = { |
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.table = &apb1_config, |
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.getter = sunxi_get_apb1_factors, |
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}; |
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static void __init sunxi_factors_clk_setup(struct device_node *node, |
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struct factors_data *data) |
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{ |
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struct clk *clk; |
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const char *clk_name = node->name; |
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const char *parent; |
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void *reg; |
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reg = of_iomap(node, 0); |
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parent = of_clk_get_parent_name(node, 0); |
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clk = clk_register_factors(NULL, clk_name, parent, CLK_IGNORE_UNUSED, |
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reg, data->table, data->getter, &clk_lock); |
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if (clk) { |
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of_clk_add_provider(node, of_clk_src_simple_get, clk); |
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clk_register_clkdev(clk, clk_name, NULL); |
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} |
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} |
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|
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/**
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* sunxi_mux_clk_setup() - Setup function for muxes |
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*/ |
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#define SUNXI_MUX_GATE_WIDTH 2 |
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struct mux_data { |
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u8 shift; |
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}; |
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static const __initconst struct mux_data cpu_data = { |
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.shift = 16, |
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}; |
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static const __initconst struct mux_data apb1_mux_data = { |
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.shift = 24, |
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}; |
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static void __init sunxi_mux_clk_setup(struct device_node *node, |
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struct mux_data *data) |
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{ |
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struct clk *clk; |
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const char *clk_name = node->name; |
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const char **parents = kmalloc(sizeof(char *) * 5, GFP_KERNEL); |
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void *reg; |
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int i = 0; |
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reg = of_iomap(node, 0); |
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while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL) |
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i++; |
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clk = clk_register_mux(NULL, clk_name, parents, i, 0, reg, |
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data->shift, SUNXI_MUX_GATE_WIDTH, |
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0, &clk_lock); |
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if (clk) { |
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of_clk_add_provider(node, of_clk_src_simple_get, clk); |
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clk_register_clkdev(clk, clk_name, NULL); |
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} |
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} |
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/**
|
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* sunxi_divider_clk_setup() - Setup function for simple divider clocks |
||||
*/ |
||||
|
||||
#define SUNXI_DIVISOR_WIDTH 2 |
||||
|
||||
struct div_data { |
||||
u8 shift; |
||||
u8 pow; |
||||
}; |
||||
|
||||
static const __initconst struct div_data axi_data = { |
||||
.shift = 0, |
||||
.pow = 0, |
||||
}; |
||||
|
||||
static const __initconst struct div_data ahb_data = { |
||||
.shift = 4, |
||||
.pow = 1, |
||||
}; |
||||
|
||||
static const __initconst struct div_data apb0_data = { |
||||
.shift = 8, |
||||
.pow = 1, |
||||
}; |
||||
|
||||
static void __init sunxi_divider_clk_setup(struct device_node *node, |
||||
struct div_data *data) |
||||
{ |
||||
struct clk *clk; |
||||
const char *clk_name = node->name; |
||||
const char *clk_parent; |
||||
void *reg; |
||||
|
||||
reg = of_iomap(node, 0); |
||||
|
||||
clk_parent = of_clk_get_parent_name(node, 0); |
||||
|
||||
clk = clk_register_divider(NULL, clk_name, clk_parent, 0, |
||||
reg, data->shift, SUNXI_DIVISOR_WIDTH, |
||||
data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, |
||||
&clk_lock); |
||||
if (clk) { |
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk); |
||||
clk_register_clkdev(clk, clk_name, NULL); |
||||
} |
||||
} |
||||
|
||||
|
||||
/* Matches for of_clk_init */ |
||||
static const __initconst struct of_device_id clk_match[] = { |
||||
{.compatible = "fixed-clock", .data = of_fixed_clk_setup,}, |
||||
{.compatible = "allwinner,sunxi-osc-clk", .data = sunxi_osc_clk_setup,}, |
||||
{} |
||||
}; |
||||
|
||||
/* Matches for factors clocks */ |
||||
static const __initconst struct of_device_id clk_factors_match[] = { |
||||
{.compatible = "allwinner,sunxi-pll1-clk", .data = &pll1_data,}, |
||||
{.compatible = "allwinner,sunxi-apb1-clk", .data = &apb1_data,}, |
||||
{} |
||||
}; |
||||
|
||||
/* Matches for divider clocks */ |
||||
static const __initconst struct of_device_id clk_div_match[] = { |
||||
{.compatible = "allwinner,sunxi-axi-clk", .data = &axi_data,}, |
||||
{.compatible = "allwinner,sunxi-ahb-clk", .data = &ahb_data,}, |
||||
{.compatible = "allwinner,sunxi-apb0-clk", .data = &apb0_data,}, |
||||
{} |
||||
}; |
||||
|
||||
/* Matches for mux clocks */ |
||||
static const __initconst struct of_device_id clk_mux_match[] = { |
||||
{.compatible = "allwinner,sunxi-cpu-clk", .data = &cpu_data,}, |
||||
{.compatible = "allwinner,sunxi-apb1-mux-clk", .data = &apb1_mux_data,}, |
||||
{} |
||||
}; |
||||
|
||||
static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match, |
||||
void *function) |
||||
{ |
||||
struct device_node *np; |
||||
const struct div_data *data; |
||||
const struct of_device_id *match; |
||||
void (*setup_function)(struct device_node *, const void *) = function; |
||||
|
||||
for_each_matching_node(np, clk_match) { |
||||
match = of_match_node(clk_match, np); |
||||
data = match->data; |
||||
setup_function(np, data); |
||||
} |
||||
} |
||||
|
||||
void __init sunxi_init_clocks(void) |
||||
{ |
||||
/* Register all the simple sunxi clocks on DT */ |
||||
of_clk_init(clk_match); |
||||
|
||||
/* Register factor clocks */ |
||||
of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); |
||||
|
||||
/* Register divider clocks */ |
||||
of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup); |
||||
|
||||
/* Register mux clocks */ |
||||
of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup); |
||||
} |
||||
@ -0,0 +1,22 @@ |
||||
/*
|
||||
* Copyright 2012 Maxime Ripard |
||||
* |
||||
* Maxime Ripard <maxime.ripard@free-electrons.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#ifndef __LINUX_CLK_SUNXI_H_ |
||||
#define __LINUX_CLK_SUNXI_H_ |
||||
|
||||
void __init sunxi_init_clocks(void); |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue